Paul Petric

REBL: design progress toward 16 nm half-pitch maskless projection electron beam lithography

REBL (Reflective Electron Beam Lithography) is a novel concept for high speed maskless projection electron beam lithography. Originally targeting 45 nm HP (half pitch) under a DARPA funded contract, we are now working on optimizing the optics and architecture for the commercial silicon integrated circuit fabrication market at the equivalent of 16 nm HP. The shift to smaller features requires innovation in most major subsystems of the tool, including optics, stage, and metrology. We also require better simulation and understanding of the exposure process. In order to meet blur requirements for 16 nm lithography, we are both shrinking the pixel size and reducing the beam current. Throughput will be maintained by increasing the number of columns as well as other design optimizations. In consequence, the maximum stage speed required to meet wafer throughput targets at 16 nm will be much less than originally planned for at 45 nm. As a result, we are changing the stage architecture from a rotary design to a linear design that can still meet the throughput requirements but with more conventional technology that entails less technical risk. The linear concept also allows for simplifications in the datapath, primarily from being able to reuse pattern data across dies and columns. Finally, we are now able to demonstrate working dynamic pattern generator (DPG) chips, CMOS chips with microfabricated lenslets on top to prevent crosstalk between pixels.

REBL nanowriter: Reflective Electron Beam Lithography

REBL (Reflective Electron Beam Lithography) is being developed for high throughput electron beam direct write maskless lithography. The system is specifically targeting 5 to 7 wafer levels per hour throughput on average at the 45 nm node, with extendibility to the 32 nm node and beyond. REBL incorporates a number of novel technologies to generate and expose lithographic patterns at estimated throughputs considerably higher than electron beam lithography has been able to achieve as yet. A patented reflective electron optic concept enables the unique approach utilized for the Digital Pattern Generator (DPG). The DPG is a CMOS ASIC chip with an array of small, independently controllable cells or pixels, which act as an array of electron mirrors. In this way, the system is capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the writing strategy of the DPG to achieve the capability of high throughput for sparse pattern wafer levels. The exposure method utilized by the DPG was emulated on a Vistec VB-6 in order to validate the gray level exposure method used in REBL. Results of these exposure tests are discussed.

Demonstration of lithography patterns using reflective e-beam direct write

Traditionally, e-beam direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the uncertainty with regards to the optical lithography roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for high volume wafer processing. For this work, we report on the development and current status of a new maskless, direct write e-beam lithography tool which has the potential for high volume lithography at and below the 22 nm technology node. A Reflective Electron Beam Lithography (REBL) tool is being developed for high throughput electron beam direct write maskless lithography. The system is targeting critical patterning steps at the 22 nm node and beyond at a capital cost equivalent to conventional lithography. Reflective Electron Beam Lithography incorporates a number of novel technologies to generate and expose lithographic patterns with a throughput and footprint comparable to current 193 nm immersion lithography systems. A patented, reflective electron optic or Digital Pattern Generator (DPG) enables the unique approach. The Digital Pattern Generator is a CMOS ASIC chip with an array of small, independently controllable lens elements (lenslets), which act as an array of electron mirrors. In this way, the REBL system is capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the writing strategy of the DPG to achieve the capability of high throughput for sparse pattern wafer levels. The lens elements on the DPG are fabricated at IMEC (Leuven, Belgium) under IMECs CMORE program. The CMOS fabricated DPG contains ~ 1,000,000 lens elements, allowing for 1,000,000 individually controllable beamlets. A single lens element consists of 5 electrodes, each of which can be set at controlled voltage levels to either absorb or reflect the electron beam. A system using a linear movable stage and the DPG integrated into the electron optics module was used to expose patterns on device representative wafers. Results of these exposure tests are discussed.

The REBL DPG: recent innovations and remaining challenges

Reflective electron-beam lithography (REBL) employs a novel device to impress pattern information on an electron beam. This device, the digital pattern generator (DPG), is an array of small electron reflectors, in which the reflectance of each mirror is controlled by underlying CMOS circuitry. When illuminated by a beam of low-energy electrons, the DPG is effectively a programmable electron-luminous image source. By switching the mirror drive circuits appropriately, the DPG can ‘scroll’ the image of an integrated circuit pattern across its surface; and the moving electron image, suitably demagnified, can be used to expose the resist-coated surface of a wafer or mask. This concept was first realized in a device suitable for 45 nm lithography demonstrations. A next-generation device has been designed and is presently nearing completion. The new version includes several advances intended to make it more suitable for application in commercial lithography systems. We will discuss the innovations and compromises in the design of this next-generation device. For application in commercially-practical maskless lithography at upcoming device nodes, still more advances will be needed. Some of the directions in which this technology can be extended will be described.

Digital pattern generator: an electron-optical MEMS for massively parallel reflective electron beam lithography

Abstract. The digital pattern generator (DPG) is a complex electron-optical MEMS that pixelates the electron beam in the reflective electron beam lithography (REBL) e-beam column. It potentially enables massively parallel printing, which could make REBL competitive with optical lithography. The development of the REBL DPG, from the CMOS architecture, through the lenslet modeling and design, to the fabrication of the MEMS device, is described in detail. The imaging and printing results are also shown, which validate the pentode lenslet concept and the fabrication process.

New advances with REBL for maskless high-throughput EBDW lithography

REBL (Reflective Electron Beam Lithography) is a program for the development of a novel approach for highthroughput maskless lithography. The program at KLA-Tencor is funded under the DARPA Maskless Nanowriter Program. A DPG (digital pattern generator) chip containing over 1 million reflective pixels that can be individually turned on or off is used to project an electron beam pattern onto the wafer. The DARPA program is targeting 5 to 7 wafers per hour at the 45 nm node, and this paper will describe improvements to both increase the throughput as well as extend the system to the 2x nm node and beyond. This paper focuses on three specific areas of REBL technology. First, a new column design has been developed based on a Wien filter to separate the illumination and projection beams. The new column design is much smaller, and has better performance both in resolution and throughput than the first column which used a magnetic prism for separation. This new column design is the first step leading to a multiple column system. Second, the rotary stage latest results of a fully integrated DPG CMOS chip with lenslets will be reviewed. An array of over 1 million micro lenses which is fabricated on top of the CMOS DPG chip has been developed. The microlens array eliminates crosstalk between adjacent pixels, maximizes contrast between on and off states, and provides matching of the NA between the DPG reflector and the projection optics.

Electron bombardment of films used for reducing spurious charge in electrostatic electron optics

In electrostatic electron optics charging on the surfaces of insulators separating the electrodes can cause undesired beam fluctuation. In prior work, the authors showed that coating the insulators with a film deposited by atomic layer deposition (ALD) could lead to acceptably low charging effects in the reflection electron beam lithography system. However, the stability of the resistivity can also be affected by contaminants present in the vacuum environment of the electron beam tool. The mechanism of formation for carbon layers typically involves the cracking of hydrocarbon contaminants adsorbed on the film surface by photon, electrons, or heat. This work describes changes in resistivity of ALD films of zinc–zirconium oxide and tantalum–niobium oxide 40 nm thick under different operating conditions. In a vacuum system utilizing an oil rough pump and a turbo pump, <0.01 C/cm2 bombardment with 309 V electrons results in about 1 order of magnitude reduction in surface resistance. This effect was not observ...

Reflective electron-beam lithography performance for the 10nm logic node

Maskless electron beam lithography has the potential to extend semiconductor manufacturing to the sub-10 nm technology node. KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL) for high-volume 10 nm logic (16 nm HP). This paper reviews progress in the development of the REBL system towards its goal of 100 wph throughput for High Volume Lithography (HVL) at the 2X and 1X nm nodes. In this paper we introduce the Digital Pattern Generator (DPG) with integrated CMOS and MEMs lenslets that was manufactured at TSMC and IMEC. For REBL, the DPG is integrated to KLA-Tencor pattern generating software that can be programmed to produce complex, gray-scaled lithography patterns. Additionally, we show printing results for a range of interesting lithography patterns using Time Domain Imaging (TDI). Previously, KLA-Tencor reported on the development of a Reflective Electron Beam Lithography (REBL) tool for maskless lithography at and below the 22 nm technology node1. Since that time, the REBL team and its partners (TSMC, IMEC) have made good progress towards developing the REBL system and Digital Pattern Generator (DPG) for direct write lithography. Traditionally, e-beam direct write lithography has been too slow for most lithography applications. Ebeam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the continued uncertainty with regards to the optical lithography roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for HVL.