Luke G. England

Reliability of Cu Wire Bonding to Al Metallization

The use of Cu wire for thermosonic ball bonding presents several advantages over Au wire. These advantages include significant cost savings due to cheaper raw material cost, higher electrical conductivity for faster die functionality, and much slower intermetallic compound (IMC) growth than Au wire. There are still some challenges that must be overcome, however, before Cu wire bonding can be successful. Since Cu is much harder than Au there is the potential to cause damage to the bond pad or other underlying layers of the die. Oxidation of the Cu wire can also act to inhibit second bond formation, which can result in increased wire bond no-stick rates. Cu oxidation can also result in a very short spool lifetime once the wire has been exposed to the atmosphere. This study focuses on the manufacturability and reliability of using Cu wire for ball bonding in a high volume DRAM production environment. Wire bonding first bond parameters were optimized, and the process was characterized through bond integrity testing (BIT). Package reliability was determined through environmental tests that included HAST, T/C-B, and HTS. IMC growth in the Al-Cu system was characterized and compared to the Al-Au system. Electrical test data of live packages bonded with Cu wire was also compared to that of packages bonded with Au wire to determine if there was any amount of performance or DRAM refresh degradation caused by the Cu wire. This was done at both the individual package level and module level.

Impact of 3D Via Middle TSV Process on 20nm Wafer Level FEOL and BEOL Reliability

The impact of after level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) and aspects. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) plots show that there is negligible impact on Idsat due to mechanical stress of the TSV for <; 3μm KOZ for both NFET and PFET devices fabricated with thin and thick gate-oxide dielectric. Voltage/Ramp Stress (VRS) and Constant Voltage Stress (CVS) tests were performed to analyze FEOL reliability for degradation phenomena such as Voltage Break Down (VBD), Hot Carrier Injection (HCI), and Bias Temperature stability (BTI). Test structures were designed to investigate TSV impact on the lower metal and via levels of the BEOL stack. BEOL reliability analysis for degradation phenomena such as Time Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and Stress Migration (SM) were performed to investigate any potential impact to due to TSV mechanical stress or Cu pumping effects. BEOL Our investigations showed no significant impact to FEOL or BEOL test structures due to the TSV via middle approach.