Lurng-Shehng Lee

Low-Power Switching of Nonvolatile Resistive Memory Using Hafnium Oxide

Nonstoichiometric hafnium oxide (HfOx) resistive-switching memory devices with low-power operation have been demonstrated. Polycrystalline HfOx (O:Hf=1.5:1) films with a thickness of 20 nm are grown on a titanium nitride (TiN) bottom electrode by commercial atomic layer deposition. Platinum (Pt) as a top electrode is used in the memory device. Voltage-induced resistance switching is repeatedly observed in the Pt/HfOx/TiN/Si memory device with resistance ratio is greater than 10. During the switching cycles, the power consumptions for high- and low-resistance states are found to be 0.25 and 0.15 mW, respectively. At 85 °C, the memory device shows stable resistance switching and superior data retention with resistance ratio is greater than 100. In addition, our memory device shows little area dependence of resistance-switching behavior. The anodic electrode containing noble metal Pt serves an important role in maintaining stable resistance switching. The resistance switching in the HfOx films is thought to be due to the defects that are generated by the applied bias. The nonstoichiometric HfOx films are responsible for the low SET and RESET currents during switching. Our study shows that the HfOx resistive-switching memory is a promising candidate for next-generation nonvolatile memory device applications.

Cerium oxide nanocrystals for nonvolatile memory applications

The characteristics of silicon-oxide-nitride-oxide-silicon-type memories embedded with cerium oxide nanocrystals were demonstrated. They were fabricated by depositing a thin CeO2 film on the SiO2 tunneling layer and subsequently rapid-thermal annealing process. The mean size and aerial density of the CeO2 nanocrystals embedded in SiO2 are estimated to be about 8–10nm and (3–7)×1011∕cm−2 after a high-temperature annealing with different ambients on 900°C. The program/erase behaviors and data retention characteristics were described to demonstrate its advantages for nonvolatile memory device applications.

Negative bias temperature instability of SiC MOSFET induced by interface trap assisted hole trapping

We investigated the negative bias temperature instability (NBTI) characteristics of 4H-SiC metal oxide semiconductor field effect transistor (MOSFET) and metal oxide semiconductor capacitor (MOSCAP). The shift of threshold voltage approached saturation with time, and the different magnitude of mid-gap voltage shift with different starting biases observed in capacitance-voltage (CV) curves taken from MOSCAP and MOSFET suggested that the hole trapping was the primary mechanism contributing to the NBTI in this study. The trend of mid-gap voltage shift with starting bias and threshold voltage shift with stress bias showed steep change before −10 V and approached saturation after −10 V which can be explained by a process where the hole trapping was assisted by positively charged interface states. The positively charged interface states may have acted as an intermediate state which reduced the overall energy barrier and facilitated the process of hole trapping. The split-CV sweeps with 0 s and 655 s of hold tim...

Demonstration of Lateral IGBTs in 4H-SiC

Lateral insulated gate bipolar transistors (IGBTs) in 4H-SiC are demonstrated for the first time. The devices were fabricated based on three different designs to investigate the effects of buffer doping and carrier lifetime on device performance. Experimental results show that, with a lightly doped buffer, a short drift region length, and an improved carrier lifetime, the common base current gain of the parasitic bipolar junction transistor (BJT) is improved, leading to a higher current capability of the IGBT. The differential on-resistance of the lateral IGBT with Ld = 20 μm is smaller than that of a lateral MOSFET counterpart, implying partial conductivity modulation in the drift region.

Low Voltage Operation of High-κ HfO2/TiO2/Al2O3 Single Quantum Well for Nanoscale Flash Memory Device Applications

Memory characteristics of the high-κ HfO2/TiO2/Al2O3 single quantum well in a p-Si/Al2O3/HfO2/TiO2/Al2O3/platinum capacitor structure have been investigated. All high-κ films have been deposited by atomic layer deposition. A significant memory window of ~1.6 V at a low gate voltage operation of 2 V, a high charge storage density of ~3.6×1012/cm2, a moderate leakage current density of 1×10-6/cm2 at a gate voltage of -2 V, and a negligible charge loss of <5% up to 104 s of retention for the high-κ HfO2/TiO2/Al2O3 single quantum well memory capacitor have been observed as compared with those of pure HfO2, pure TiO2, and pure Al2O3 charge trapping layers. Excellent memory characteristics of the high-κ HfO2/TiO2/Al2O3 single quantum well device are obtained due to charge storage in the quantum well. The high-κ HfO2/TiO2/Al2O3 quantum well device with a low gate voltage operation of <2 V can be used in future nanoscale flash memory device applications.

Schottky barrier height modification of metal/4H-SiC contact using ultrathin TiO2 insertion method

The fabrication processes, electrical characteristics, and reliability of the Schottky barrier diodes (SBDs) on an n-type 4H-silicon carbide (SiC) substrate are investigated. To modulate the Schottky barrier height (SBH), titanium dioxide (TiO2) is inserted at the interface between the metal and the SiC substrate. Ni, Mo, Ti, and Al are chosen to form SBDs. The maximum SBH modulation of 0.3 eV is obtained with a 5-nm-thick TiO2 layer. The SBH pinning factors of the SBDs without TiO2 insertion and with 2-nm-thick TiO2 insertion are similar. Therefore, the mechanism of the SBH modulation is attributed to the interface dipole-induced potential drop. Finally, the reliability of the SBD with TiO2 insertion is evaluated. The SBH, ideality factor, and reverse leakage current are stable after high forward current stress at 300 A/cm2 for 15000 s. This work provides a simple method to modulate the SBH on SiC and is feasible for SBD application.

TiO2 Nanocrystal Prepared by Atomic-Layer-Deposition System for Non-Volatile Memory Application

TiO2 nanocrystals were successfully fabricated using an atomic-layer-deposition (ALD) system. A TiN/Al2O3-laminated structure was employed as a starting structure, and after appropriate annealing, TiN was oxidized and TiO2 nanocrystals were formed. Experimental results indicate that rapid thermal annealing (RTA) temperature and annealing time are very critical factors. Also, the thickness of each TiN layer in the TiN/Al2O3-laminated starting structure is critical for TiO2 nanocrystal formation. Capacitance–voltage (C–V) measurement evidenced that an optimal annealing condition exists and an optimal annealing temperature and annealing time mainly depend on the thickness of each TiN layer in the TiN/Al2O3-laminated starting structure.

Physical and reliability characteristics of Hf-based gate dielectrics on strained-Si/sub 1-x/Ge/sub x/ MOS devices

The physical and reliability characteristics of strained-Si/sub 0.8/Ge/sub 0.2/ MOS capacitor and strained-Si/sub 0.7/Ge/sub 0.3/ MOSFET with Hf-based gate dielectrics prepared by atomic layer chemical vapor deposition are investigated. The thickness and composition of the gate dielectrics are measured by high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy, respectively. The gate leakage current and interface traps of HfO/sub 2//Si/sub 1-x/Ge/sub x/ gate structure are slightly higher as compared to the HfO/sub 2//Si MOS devices, which is basically caused by the Ge at the interface. The electrical properties of both HfO/sub 2//Si and HfO/sub 2//Si/sub 1-x/Ge/sub x/ devices can be improved with increasing PDA temperature up to 800/spl deg/C, which is due to the thicker interfacial layer grown at the interface, even though crystallization also grows with increasing temperature. However, with higher PDA temperature (>800/spl deg/C), serious crystallization of HfO/sub 2/ film causes more bulk traps induced electrical degradation. The electrical stress induced degradation of Si/sub 1-x/Ge/sub x/ substrate is slightly higher as compared to the control Si, due to more traps generations at the HfO/sub 2//Si/sub 1-x/Ge/sub x/ interface. For MOSFET, strained-Si/sub 1-x/Ge/sub x/ can effectively improve the drain current for about 20% at saturation and 69% at linear region. The higher gate leakage (J/sub g//spl sim/1.4/spl times/10/sup -9/A/cm/sup 2/ at 2 V) and lower breakdown voltage (BD/spl sim/3.1 V) of Si/sub 0.7/Ge/sub 0.3/ pMOS devices are observed as compared to control Si devices (J/sub g//spl sim/7.9/spl times/10/sup -12/A/cm/sup 2/ at 2 V and BD/spl sim/7.4 V). After the electrical stress, the degradation of drain current and transconductance and the shift of threshold voltage for Si/sub 1-x/Ge/sub x/ PMOSFET are larger than those for control Si devices, implying Ge induced trap generation at the Hf-silicate/Si/sub 1-x/Ge/sub x/ interface.

1700V/30A 4H-SiC MOSFET with low cut-in voltage embedded diode and room temperature boron implanted termination

In this paper, a SiC MOSFET embedded with a low cut-in voltage Schottky diode was proposed. The 1V cut-in voltage of embedded Schottky diode, which is lower than the 3V cut-in voltage of parasitic body diode, can prevent the potential failures caused by the transformation of dislocation defects into stacking faults due to the recombination of injected minority carriers when parasitic body diode in SiC MOSFET was turned on. The voltage drop of forward biased embedded diode at a current density of 75 A/cm2 is 1.7V, compared to the 4.9V in the parasitic body diode, is helpful to reduce the energy loss. The terminations with floating guard rings formed by aluminum implantations at 500°C and an extended coupling band formed by boron implantations at room temperatures were able to achieve a blocking voltage of up to 1889V with a drift layer of 11μm thickness and 6×1015 cm-3 doping concentration. This termination provided a very tight distribution of blocking voltages with an average value of 1797V and a sigma of 43V or a mean to sigma value of only 2.4%, for 28 devices across the wafer. The working of the extended coupling band formed by room temperature implantation is speculated different from the ordinary junction termination extension (JTE) as the single zone JTEs formed by the room temperature boron implantations could provide blocking voltages of about 500V, which is essentially of the same level for devices without terminations. A highly resistive region formed due to unrecoverable damages caused by room temperature implantations was considered to provide stable coupling between guard rings and thus improve the blocking voltage.

HfO2/HfAlO/HfO2 Nanolaminate Charge Trapping Layers for High-Performance Nonvolatile Memory Device Applications

A high-κ HfO2/HfAlO/HfO2 nanolaminate charge trapping layer in a p-Si/SiO2/[HfO2/HfAlO/HfO2 nanolaminate]/Al2O3/platinum memory capacitor has been investigated. High-κ HfO2, Al2O3, and HfO2/HfAlO/HfO2 nanolaminate charge trapping layers are deposited by atomic layer deposition. Well-behaved counter clockwise capacitance–voltage hysteresis characteristics are observed for all memory capacitors. A large memory window of ~10 V, a very low leakage current density of ~5×10-9 A/cm2 at a gate voltage of -5 V, a high charge trapping density of ~1.6×1013/cm2, and a low charge loss of ~20% after 10 years of retention for the HfO2/HfAlO/HfO2 nanolaminate charge trapping layer are observed as compared with those of pure HfO2 and pure Al2O3 charge trapping layers. Excellent memory characteristics of HfO2/HfAlO/HfO2 nanolaminate layers are obtained owing to the layer-by-layer charge storage. High-κ HfO2/HfAlO/HfO2 nanolaminate charge trapping layers can be used in future nanoscaled high-performance nonvolatile memory device applications.