Cha-Hsin Lin

Low-Power Switching of Nonvolatile Resistive Memory Using Hafnium Oxide

Nonstoichiometric hafnium oxide (HfOx) resistive-switching memory devices with low-power operation have been demonstrated. Polycrystalline HfOx (O:Hf=1.5:1) films with a thickness of 20 nm are grown on a titanium nitride (TiN) bottom electrode by commercial atomic layer deposition. Platinum (Pt) as a top electrode is used in the memory device. Voltage-induced resistance switching is repeatedly observed in the Pt/HfOx/TiN/Si memory device with resistance ratio is greater than 10. During the switching cycles, the power consumptions for high- and low-resistance states are found to be 0.25 and 0.15 mW, respectively. At 85 °C, the memory device shows stable resistance switching and superior data retention with resistance ratio is greater than 100. In addition, our memory device shows little area dependence of resistance-switching behavior. The anodic electrode containing noble metal Pt serves an important role in maintaining stable resistance switching. The resistance switching in the HfOx films is thought to be due to the defects that are generated by the applied bias. The nonstoichiometric HfOx films are responsible for the low SET and RESET currents during switching. Our study shows that the HfOx resistive-switching memory is a promising candidate for next-generation nonvolatile memory device applications.

Forming-free HfO 2 bipolar RRAM device with improved endurance and high speed operation

A forming-free resistive memory of TiN/Ti/HfO2/TiN with a thin HfO2 film is demonstrated. The as-fabricated device can be operated without additional forming step to initiate the operation. This device with bipolar operation mode shows high speed (∼ 10 ns), robust endurance (≫ 106 times), good data retention (10-year lifetime), enough resistance ratio, and low power consumption. The simple structure and capability of multi-level operation demonstrate RRAM as a high-density memory in the near future.

Process integration of 3D Si interposer with double-sided active chip attachments

A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of the passive interposer, double-sided chip assembly process, and passive electrical characterization.

Effects of Slurry in Cu Chemical Mechanical Polishing (CMP) of TSVs for 3-D IC Integration

In this paper, the optimization of Cu chemical-mechanical polishing (CMP) performance (dishing) for the removal of thick Cu-plating overburden due to Cu plating for deep through silicon via (TSV) in a 300-mm wafer is investigated. Moreover, backside isolation oxide CMP for TSV Cu exposure is examined. To obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu-polishing process. First, a bulk of Cu is removed with the slurry of high Cu removal rate and second, the Cu surface is planarized with the slurry of high Cu passivation capability. The Cu dishing can be improved up to 97% for the 10-μm-diameter TSVs on a 300-mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly optimized Cu-plating overburden for TSVs and redistribution layers. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a larger TSV diameter still keep in a plateau-like shape after CMP.

Low Voltage Operation of High-κ HfO2/TiO2/Al2O3 Single Quantum Well for Nanoscale Flash Memory Device Applications

Memory characteristics of the high-κ HfO2/TiO2/Al2O3 single quantum well in a p-Si/Al2O3/HfO2/TiO2/Al2O3/platinum capacitor structure have been investigated. All high-κ films have been deposited by atomic layer deposition. A significant memory window of ~1.6 V at a low gate voltage operation of 2 V, a high charge storage density of ~3.6×1012/cm2, a moderate leakage current density of 1×10-6/cm2 at a gate voltage of -2 V, and a negligible charge loss of <5% up to 104 s of retention for the high-κ HfO2/TiO2/Al2O3 single quantum well memory capacitor have been observed as compared with those of pure HfO2, pure TiO2, and pure Al2O3 charge trapping layers. Excellent memory characteristics of the high-κ HfO2/TiO2/Al2O3 single quantum well device are obtained due to charge storage in the quantum well. The high-κ HfO2/TiO2/Al2O3 quantum well device with a low gate voltage operation of <2 V can be used in future nanoscale flash memory device applications.

Microstructural Evolution of Metal–Insulator–Metal Capacitor Prepared by Atomic-Layer-Deposition System at Elevated Temperature

The rougher surface and raised-hollow holes were observed in the TiN/Al2O3/HfO2/Al2O3/TiN/SiO2/Si multi-stack metal–insulator–metal (MIM) capacitor sample after 1000 °C, 60 s rapid thermal annealing (RTA) process in N2. The surface became rougher partially resulted from the nucleation of TiN layer after RTA. Experimental results also indicated that the oxygen content in the HfO2 was desorbed and the remaining Hf was crystallized. Also, the TiN and Al2O3 layers were intermixed and partially re-crystallized at this high temperature. Very clear morie fringes could be observed in the high-resolution transmission electron microscopy (HR-TEM) micrographs. Also, the energy dispersive spectroscopy (EDS) results indicated that the nitrogen in TiN was desorbed and the TiN was phase transformed to TiO2. This phenomenon might result from the TiN oxidation process during the high-temperature thermal annealing.

TiO2 Nanocrystal Prepared by Atomic-Layer-Deposition System for Non-Volatile Memory Application

TiO2 nanocrystals were successfully fabricated using an atomic-layer-deposition (ALD) system. A TiN/Al2O3-laminated structure was employed as a starting structure, and after appropriate annealing, TiN was oxidized and TiO2 nanocrystals were formed. Experimental results indicate that rapid thermal annealing (RTA) temperature and annealing time are very critical factors. Also, the thickness of each TiN layer in the TiN/Al2O3-laminated starting structure is critical for TiO2 nanocrystal formation. Capacitance–voltage (C–V) measurement evidenced that an optimal annealing condition exists and an optimal annealing temperature and annealing time mainly depend on the thickness of each TiN layer in the TiN/Al2O3-laminated starting structure.

HfO2/HfAlO/HfO2 Nanolaminate Charge Trapping Layers for High-Performance Nonvolatile Memory Device Applications

A high-κ HfO2/HfAlO/HfO2 nanolaminate charge trapping layer in a p-Si/SiO2/[HfO2/HfAlO/HfO2 nanolaminate]/Al2O3/platinum memory capacitor has been investigated. High-κ HfO2, Al2O3, and HfO2/HfAlO/HfO2 nanolaminate charge trapping layers are deposited by atomic layer deposition. Well-behaved counter clockwise capacitance–voltage hysteresis characteristics are observed for all memory capacitors. A large memory window of ~10 V, a very low leakage current density of ~5×10-9 A/cm2 at a gate voltage of -5 V, a high charge trapping density of ~1.6×1013/cm2, and a low charge loss of ~20% after 10 years of retention for the HfO2/HfAlO/HfO2 nanolaminate charge trapping layer are observed as compared with those of pure HfO2 and pure Al2O3 charge trapping layers. Excellent memory characteristics of HfO2/HfAlO/HfO2 nanolaminate layers are obtained owing to the layer-by-layer charge storage. High-κ HfO2/HfAlO/HfO2 nanolaminate charge trapping layers can be used in future nanoscaled high-performance nonvolatile memory device applications.

Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer

TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical polishing) to remove the SiN/SiO2 and the Cu and seed/barrier layers of the Cu-filled TSV. On the other hand, for the via-last from the backside process, a carrier is temporary bonded on the frontside of the “finished” wafer (which includes all the metal layers, pads and passivation) and backgrind the backside of the wafer to ≤50 μm thick. TSVs and RDLs (redistribution layers) are formed from the backside of the wafer by the dual-damascene process. There are at least 3 challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer, namely (a) the residues in the dies due to the excess of TTV (total thickness variation) resulting from the degassing/deformation of glue during temporary bonding; (b) the residues on wafer edge due to the low down force during CMP to avoid the thin wafer chipping; and (c) Cu residues along the recess areas of the grinding traces during wafer thinning process. In this study, the processes are developed to overcome these three challenges. Specifically, the Cu residues in the dies are reduced substantially by choosing a thermosetting glue over a thermoplastic glue; the edge metal residues are eliminated by the process with a low down force to avoid the chipping of the thin wafer but increasing the time of Cu over-polishing in the high Cu rate slurry and avoiding Cu corrosion; and the Cu residues along the recess areas of grinding traces are resolved by Cu over-polishing using the high passivation Cu slurry to remove the Cu on the recess areas.

Key enabling technologies of 300mm 3DIC process integration

Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.