M. Breitwisch

Device, circuit and system-level analysis of noise in multi-bit phase-change memory

We present a comprehensive investigation of noise in multi-bit phase-change memory (PCM). The impact of noise on data integrity was quantified with a combination of experiments and simulations. A prototype chip was fabricated to support our system-level analysis, which shows that a raw bit error rate of ∼10−4 is achievable at 3-bit/cell. At the circuit level, we identified the bit line capacitance and the voltage regulator noise as the critical elements determining the electronic readout circuit noise. In addition, device-level measurements showed that 80% of the total noise can be traced back to the fluctuations in the PCM cell current itself. Our analysis captures for the first time how these fluctuations ultimately limit the achievable bit error rate in future multi-level-cell (MLC) PCM chips.

A high performance phase change memory with fast switching speed and high temperature retention by engineering the Ge x Sb y Te z phase change material

Phase change memory has long suffered from conflicting material properties between switching speed and thermal stability. This study explores the engineering of GeSbTe ternary alloys along an isoelectronic tie line and the Ge/Sb2Te3 tie line with the hope of finding a high performance material. Our efforts resulted in a new material that considerably outperforms the conventional GST-225. The switching speed is similar to undoped GST-225, with ∼ 30% lower reset current, and nearly 100°C higher Tx, thus much better thermal stability. The promising properties of this new material are demonstrated in a 128Mb chip and tested both at wafer level and as packaged dies. These devices showed 1E8 cycling endurance and withstood 190 °C testing.

Drift-resilient cell-state metric for multilevel phase-change memory

A new cell-state metric is proposed for multilevel phase-change memory (PCM) that is more representative of the fundamental programmed entity, i.e., the amorphous/crystalline phase configuration in the PCM cell. This metric exhibits improved performance in terms of drift and better sensing resolution of cell states with a large amorphous-phase fraction when compared to the conventional low-field resistance metric. Experimental results using PCM test devices of mushroom type demonstrate the efficacy of the new metric.

On the dynamic resistance and reliability of phase change memory

A novel characterization metric for phase change memory based on the measured cell resistance during RESET programming is introduced. We show that this dasiadynamic resistancepsila (Rd) is inversely related to the programming current (I), as Rd = [A/I] + B. While the slope parameter A depends only on the intrinsic properties of the phase change material, the intercept B also depends on the effective physical dimensions of the memory element. We demonstrate that these two parameters provide characterization and insight into the degradation mechanisms of memory cells during operation.

Understanding amorphous states of phase-change memory using Frenkel-Poole model

A method based on Frenkel-Poole emission is proposed to model the amorphous state (high resistance state) in mushroom-type phase-change memory devices. The model provides unique insights to probe the device after amorphizing (RESET) operation. Even when the resistance appears the same under different RESET conditions, our model suggests that both the amorphous region size and the defect states are different. With this powerful new tool, detailed changes inside the amorphous GST for MLC operation and retention tests are revealed.

Mechanisms of retention loss in Ge 2 Sb 2 Te 5 -based Phase-Change Memory

Data retention loss from the amorphous (RESET) state over time in Phase-Change Memory cells is associated with spontaneous crystallization. In this paper, the change in the threshold voltage (VT) of memory cells in the RESET state before and after heating is used as a probe into the nature of the retention loss mechanisms. Two mechanisms for the retention loss behavior are identified, responsible for the main distribution and the tail distribution, respectively. Experimental results suggest that (i) an optimized RESET operation produces a fully amorphized Ge2Sb2Te5 (aGST) active region, with no crystalline domains inside, (ii) cells in the tail distribution fail to retain their RESET state due to spontaneous generation of crystallization nuclei and grain growth, and (iii) cells in the main distribution fail due to grain growth from the amorphous/crystalline GST boundary, instead of nucleation within the active region.

Noise margin and leakage in ultra-low leakage SRAM cell design

Various aspects of ultra-low leakage static random-access memories (SRAM) cell design are considered. It is shown that the high threshold voltage relative to the power supply so improves the stability of the cell that the beta ratio of the design may be made very small for improved performance. Also, the ramifications of threshold uncertainty due to random dopant fluctuations are investigated, and it is shown that chip performance will be adversely affected by this phenomenon.

Analytical model for RESET operation of Phase Change Memory

We present a novel analytical model for the RESET operation of Phase Change Memory (PCM) that explicitly describes the dependency of the programming current on various cell dimensions and material parameters. This model also explains, for the first time, the fundamental physics behind the inverse relationship between dynamic resistance(Rd) and the amplitude of the programming current.

Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory

The resistance of phase-change-memory (PCM) cells measured during RESET programming (dynamic resistance, Rd) is found to be inversely proportional to the amplitude of the programming current, as Rd = [A/I] + B. We show that parameters A and B are related to the intrinsic properties of the memory cell, and demonstrate by means of experimental data that they could be used to characterize the cell-to-cell process-induced variability of PCM cells.

The impact of hole-induced electromigration on the cycling endurance of phase change memory

The high current density induced failure in Ge2Sb2Te5(GST)-based phase change memory (PCM) is investigated. A strong dependence of cycling endurance on the polarity of the operation current is observed and reported for the first time. The cycling endurance is reduced by 4 orders of magnitude when the current polarity is reversed. Careful TEM analysis of failed cells revealed a thin void in GST over the bottom electrode, but only in the reverse polarity samples. This phenomenon can be explained by hole-induced electromigration at the electrode/GST interface. The impact of electromigration on scaled phase change memory is discussed.