M. de Potter

Ni- and Co-based silicides for advanced CMOS applications

The scaling behavior of Co, Co-Ni and Ni silicides to sub-40 nm gate length CMOS technologies with sub-100 nm junction depths was evaluated. Limitations were found for Co and Co-Ni alloy silicides, which exhibited an increase in sheet resistance at gate lengths below 40 nm and required high processing temperatures to achieve low junction leakage. Ni silicide was shown, in contrast, to have good scaling behavior, with a decrease in sheet resistance for decreasing gate lengths down to 30 nm, lower diode leakage (at similar sheet resistance) and lower silicide to p+ Si contact resistance than Co silicide. Key material issues impacting the applicability of NiSi to CMOS technologies were investigated. Studies of the kinetics of Ni2Si growth were used to design a process that avoids excessive silicidation of small features. The thermal degradation mechanisms of NiSi films were also studied. Thin films degraded morphologically with activation energies of ∼ 2.4 eV. Thick films degraded morphologically at low temperatures and by transformation to NiSi2 at high temperatures, suggesting a higher activation energy for the latter mechanism. Pt alloying was shown to help stabilize NiSi films against morphological degradation.

Silicides for the 100-nm node and beyond: Co-silicide, Co(Ni)-silicide and Ni-silicide

As scaling progresses, conventional Co/Ti silicidation is facing difficulties related to the nucleation of the low resistive Co-disilicide phase during the second RTP step of silicidation. When linewidths, junction depths and silicide thicknesses are being reduced, the RTP2 thermal process window narrows down rapidly. It is expected that the process window can be widened by alloying the Co film with Ni, because the presence of Ni lowers the nucleation barrier for the Co-disilicide phase. Replacing Co-disilicide by Ni-monosilicide is a promising alternative because the same silicide sheet resistance can be obtained with 35% less silicon consumption.

Self-aligned CoSi/sub 2/ for 0.18 /spl mu/m and below

CoSi/sub 2/ is being used commonly for the advanced IC technologies. There are several process choices to be made for the formation of a high yielding and reproducible silicide. In this paper the various CoSi/sub 2/ technologies are discussed. The scalability of the process of record, the Co/Ti(cap) process are presented for 0.18 /spl mu/m and below.

Comparative study of Ni-silicide and Co-silicide for sub 0.25-mm technologies

In this work, the phase formation is compared for Ni- and Co-silicidation with and without Ti cap. In addition, the electrical performance of Ni-silicidation with and without Ti-cap is investigated and compared to the performance of a Co-silicidation process with a Ti cap that has the same Si consumption. The lateral confinement of the silicide in the active areas is also studied.

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

We demonstrate for the first time CMOS integration of dual WF (work function) metal gates on HfSiON using Ni-phase controlled FUSI. The novel integration scheme that we demonstrate uses our optimized 2-step Ni FUSI process (1) for simultaneous full silicidation of nMOS and pMOS, achieving different Ni/Si ratios on nMOS and pMOS by reduction of the pMOS poly height through a selective and controlled poly etch back prior to gate silicidation. This novel integration scheme offers the advantages of 1) simplicity (same Ni deposition and silicidation process on nMOS and pMOS), 2) large process window for poly etch-back process (same pMOS characteristics for poly thickness variation of 50%), 3) WF and Vt tuning on HfSiON by phase control, with 4) scalable, linewidth independent suitable Vts for nMOS (0.5 V) and pMOS (-0.3 V), and 5) solves process yield issues of Ni-rich silicides related to volume expansion, stress, filaments and voiding, resulting in a continuous silicide that is nicely confined between the sidewall spacers. Ring oscillator operation was also demonstrated

Silicide and Shallow Trench Isolation line width dependent stress induced junction leakage

For the first time, the influence of the mechanical stress, induced by silicidation of active areas in combination with stress from the Shallow Trench Isolation (STI), on the leakage current of n+/p and p+/n junctions has been studied. When scaling down the width of the diode structure from 2 /spl mu/m to 0.25 /spl mu/m, the anisotropic compressive stress in the junction area increases drastically. These experiments prove that regardless the contributions of the area and the perimeter to the total leakage current of this type of diode structure (=20%), 80% of the total leakage current of this diode structure can be attributed to stress and that this part of the leakage current increases with almost a factor of two when reducing the junction width from 2 /spl mu/m to 0.25 /spl mu/m. Therefore, in order to keep the diode leakage variation as low as possible when further down scaling the junction and the trench dimensions, the formation of a low stress silicide in combination with a low stress isolation technology is essential.

Optimized thermal processing for Ti-capped CoSi 2 for 0.13 mm technology

Abstract CoSi2 formed using a Ti cap has been shown to reduce any oxide or contaminants present during silicide growth to improve the uniformity of the silicide. However, as transistor dimensions shrink, a concern in using CoSi2 is the thermal process window for the second RTP step (RTP2). Thinner silicides agglomerate at lower temperatures but a minimum temperature is required for a uniform silicide with low junction leakage. This paper describes the results of a detailed investigation into the thermal processing of thin Ti-capped CoSi2 compatible with 0.13 μm CMOS technology. Ti-capped CoSi2 films of varying thickness on both poly and active regions were studied for three junction dopants, As, BF2, and B. The parameters investigated in the thermal processing were the temperature, time and ramp rates for RTP2. Sheet resistance, diode leakage, and interface roughness were measured as a function of the thermal processing. The results show that the optimal RTP2 thermal budget for thin Ti-cap CoSi2 on devices is 800°C for 120 s with high ramp rates giving possible leakage improvement.

Manufacturability Issues for Application of Silicides In 0.25 μm CMOS Process and Beyond

Key issues associated with the self-aligned silicide technology, such as formation of silicides on narrow poly gate, shallow silicided junction formation, gate to source/drain bridging, and interface contact resistance, are discussed. The comparison of important technological aspects for TiSi 2 and CoSi 2 is presented. The emphasis of this work is focused on the CoSi 2 salicide technology with different variations, namely conventional process, Co/Ti capping process, and Ti/Co process. Based on the experimental results, CoSi 2 should be considered as an attractive alternative to TiSi 2 for the applications in sub-0.25 μm ULSI integrated circuits.

The influence of capping layer type on cobalt salicide formation in films and narrow lines

The effect of capping layer (Ti vs TiN) on CoSi formation and CoSi 2 sheet resistance has been investigated. Resistance measurements and XTEM analysis have been used to show that the Ti cap lowers the activation energy for CoSi formation by gettering the O 2 from the RTA (rapid thermal anneal) ambient and eliminating the formation of SiO 2 between the growing CoSi and the Co. The sheet resistance of cobalt silicide formed from Co/Ti and Co/TiN bilayers on poly- Si lines was measured as a function of linewidth and RTA temperature. With a Ti cap, the sheet resistance is low and independent of temperature, and the RTA process window is large.

Mössbauer study of the microscopic surrounding of co atoms implanted in si and ge below the full amorphization limit

Abstract Mossbauer spectroscopy on 57Co implanted into Si and Ge at doses between 1011 and 1015 atoms/cm2 supports the single track amorphization model. Calculations based on linear cascade theory do not give quantitative agreement with the experiment.