M. H. van der Veen

Electroless Cu seed on Ru and Co liners in high aspect ratio TSV

High aspect ratio through-silicon vias (3 μm diameter by 50 μm depth) have been filled by standard Cu plating process on electroless deposited (ELD) Cu seed layers on conformal liners of Ru or Co. The in-field Cu overburden that was needed to achieve electrochemical fill on the ELD-Cu seed was 600 nm. This is much lower than would have been needed in a conventional scheme with a PVD-Cu seed (of ~ 1500 nm) and, with that, reduces the Cu CMP time. This work shows the feasibility of Cu electroless as deposition technique in a TSV metallization process.

Reliability study on cobalt and ruthenium as alternative metals for advanced interconnects

Cobalt and ruthenium are being proposed to replace copper in BEOL interconnects. Using intrinsic TDDB studies, we show that Co needs a barrier to prevent it from drifting into SiO2, where for Ru no drift into any of the three studied dielectrics is observed. Although our intrinsic EM studies on single damascene lines filled with Co suffered from bondpad delamination and a non-optimized CMP, we could still conclude that the EM-performance is better compared to Cu filled lines, where a much better performance of Ru filled lines is demonstrated (>25x). Via failures on Ru schemes show a >5x higher lifetime compared to Cu schemes.

Demonstration of a cost effective Cu electroless TSV metallization scheme

In this work, we present a cost effective Cu electroless (ELD-Cu) metallization scheme in which through-silicon vias (TSVs), can be scaled towards higher aspect ratios. We successfully integrated 30 nm ELD-Cu on 15 nm Ru in 3×50 μm TSVs on 300 mm wafer scale and found excellent electrical reliability. Cost calculations revealed the major impact of the implementation of the platable Ru liner material on the costs for the deposition and chemical mechanical polishing part of the TSV metallization. In addition, we demonstrated a complete TSV filling for the 3.5 nm ALD-Ru case and investigated different kinds of Cu electrodeposition chemistries and their influence on the presence of micro-voids in the TSVs.

Void nucleation and growth during electromigration in 30 nm wide Cu lines: Impact of different interfaces on failure mode

We investigate void nucleation and growth during electromigration in 30 nm half pitch Cu lines. Diffusion interfaces are varied a) by using SiCN dielectric cap or a CoWP metal cap and b) by tuning the thickness of TaN/Ta barrier metal. The developed local sense EM test method and in-situ EM observations allow understanding void nucleation and growth stages. For the SiCN cap, independent of barrier thickness, there are two void growth modes sensitive to grain structure. In contrast, for the CoWP cap, a single mode independent of the grain structure is observed, where a nucleated void is pinned in the test line. We also show that Co diffuses into the interface between the barrier metal and Cu, and suppresses Cu diffusivity at that interface. As both Cu diffusivities at the cap and barrier interfaces are suppressed by the presence of Co, a CoWP cap is beneficial to electromigration for advanced interconnects where thinner barrier metals are required.

On-chip interconnect trends, challenges and solutions: How to keep RC and reliability under control

Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these challenges simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.

CVD-Mn/CVD-Ru-based barrier/liner solution for advanced BEOL Cu/Low-k interconnects

Aggressive downscaling of the barrier/liner thickness is the key to meet line and via resistance requirements from 15nm metal half pitch and below interconnects. For this purpose, porous low-k(2.4) dielectric/Mn-based barrier/Ru-liner/Cu system was extensively studied. Mn-silicate (MnSiO3) formation, intrinsic Cu diffusion barrier property and O2 barrier efficiency of the system were demonstrated. A stack of 1nm Mn-based barrier/1nm Ru liner was successfully integrated in tight pitch dual damascene (DD) Cu wires and its extendibility to at least 15nm feature size was confirmed both morphologically and electrically. Although, it was shown that Mn/Ru-based system is intrinsically reliable from electro-migration (EM) perspective, the absence of the flux divergence at the via bottom was also established, which needs to be addressed. Overall, this work shows that the Mn/Ru-based system is a serious barrier/liner solution for future technology nodes.

N5 technology node dual-damascene interconnects enabled using multi patterning

We demonstrate an integration approach to enable 16nm half-pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho-Etch (LE3) and tone-inversion. A silicon-verified DOE experiment on a SAQP process suggests a tight process window for core etch and spacer depositions. We also show a novel process flow which enable us to pattern tight-pitch metal-cut (block), and effectively scale the trench CD to 12nm at pitch 32nm. Finally we discuss line resistance and resistivity obtained for the 16nm and 12nm trenches created using 193i integration flow.

Study of electromigration mechanisms in 22nm half-pitch Cu interconnects by 1/f noise measurements

The electromigration (EM) performance of Cu interconnects with different barrier/liner combinations is studied by means of 1/f (or generally known as low-frequency) noise measurements. It is shown that Cu interconnects with a TaN barrier and Co liner have lower EM activation energies for 22nm half-pitch line-widths than Ru based liners. Indeed, interconnects with a 1nm Ru liner (both with TaN and Mn-based barriers) are found to outperform lines with a Co liner in terms of EM reliability. A possible explanation for this is a less defective Cu/Ru interface as compared to Cu/Co.