O. Varela Pedreira

Cu pumping in TSVs: Effect of pre-CMP thermal budget

Abstract When Cu ‘Through-Silicon-Vias’ (TSVs) are exposed to high temperatures as typically encountered during the back-end of line (BEOL) processing, the higher coefficient of thermal expansion (CTE) of Cu forces it to expand more than Si. This causes compressive stress in the confined Cu inside the TSV. This stress can partly be released near the top of the TSV, by out-of-plane expansion of the Cu, the so-called ‘Cu pumping’. It can severely damage the BEOL layers. In this paper the effect of a pre-CMP thermal budget (temperature and time) on Cu pumping is studied for various Cu chemistries and TSV aspect ratios. It is shown that to suppress Cu pumping a pre-CMP anneal is required that is either very long or at a temperature very close to the maximum temperature used in the BEOL processing.

Barrier/liner stacks for scaling the Cu interconnect metallization

Self-forming barriers and advanced liner materials are studied extensively for their Cu gapfill performance and interconnect scaling. In this paper, 22nm1/2 pitch Cu low-k interconnects with barrier (Mn-based, TaN) /liner (Co, Ru) combinations are compared and benchmarked for their resistivity, resistance scaling, and electromigration (EM) performance. Extendibility to 16nm copper width was explored experimentally and a projection towards 12nm width is performed. It is found that the Ru-liner based systems show a higher overall Cu-resistivity. We show that this increase can be compensated by combining Ru with a thinner Mn-based barrier, which increases the effective Cu-area at a particular trench width. The EM performance reveals that the Ru-liner systems have a better EM lifetime compared to the Co-liner based systems. More interestingly, in a comparison of the maximum current density Jmax a significant improvement is found for the scaled Mn-based/Ru system, making it therefore a serious candidate to extend the Cu metallization.

Impact of oxide liner properties on TSV Cu pumping and TSV stress

We investigated the impact of oxide liner elastic modulus and thickness on through-silicon via (TSV) Cu pumping and stress. A low-k dielectric liner showed a decrease in residual Cu pumping and TSV stress compared to O3-TEOS SiO2 and ALD SiO2 liners. For TSVs with a post-plating anneal, residual Cu pumping decreases from (102 ± 7) nm to (11 ± 1) nm (99.9th percentile) when the O3-TEOS SiO2 liner thickness increases from 50 to 630 nm, while the TSV stress increases from 220 to 610 MPa. The latter is attributed to permanent liner densification under compressive thermal stress at high temperature. This liner densification generates a significant part of the room temperature TSV stress. For our O3-TEOS SiO2 liner system, this was estimated to be 50 % of the total stress for a liner of 100 nm, and 90 % for a liner of 200 nm.

Reliability study on cobalt and ruthenium as alternative metals for advanced interconnects

Cobalt and ruthenium are being proposed to replace copper in BEOL interconnects. Using intrinsic TDDB studies, we show that Co needs a barrier to prevent it from drifting into SiO2, where for Ru no drift into any of the three studied dielectrics is observed. Although our intrinsic EM studies on single damascene lines filled with Co suffered from bondpad delamination and a non-optimized CMP, we could still conclude that the EM-performance is better compared to Cu filled lines, where a much better performance of Ru filled lines is demonstrated (>25x). Via failures on Ru schemes show a >5x higher lifetime compared to Cu schemes.

CVD-Mn/CVD-Ru-based barrier/liner solution for advanced BEOL Cu/Low-k interconnects

Aggressive downscaling of the barrier/liner thickness is the key to meet line and via resistance requirements from 15nm metal half pitch and below interconnects. For this purpose, porous low-k(2.4) dielectric/Mn-based barrier/Ru-liner/Cu system was extensively studied. Mn-silicate (MnSiO3) formation, intrinsic Cu diffusion barrier property and O2 barrier efficiency of the system were demonstrated. A stack of 1nm Mn-based barrier/1nm Ru liner was successfully integrated in tight pitch dual damascene (DD) Cu wires and its extendibility to at least 15nm feature size was confirmed both morphologically and electrically. Although, it was shown that Mn/Ru-based system is intrinsically reliable from electro-migration (EM) perspective, the absence of the flux divergence at the via bottom was also established, which needs to be addressed. Overall, this work shows that the Mn/Ru-based system is a serious barrier/liner solution for future technology nodes.

Correlation between stress-induced leakage current and dielectric degradation in ultra-porous SiOCH low-k materials

Stress-Induced Leakage Current (SILC) behavior during the dielectric degradation of ultra-porous SiOCH low-k materials was investigated. Under high voltage stress, SILC increases to a critical value before final hard breakdown. This SILC increase rate is mainly driven by the injected charges and is negligibly influenced by temperature and voltage. SILC is found to be transient and shows a t−1 relaxation behavior, where t is the storage time at low voltages. This t−1 transient behavior, described by the tunneling front model, is caused by both electron charging of neutral defects in the dielectric close to the cathode interface and discharging of donor defects close to the anode interface. These defects have a uniform density distribution within the probed depth range, which is confirmed by the observed flat band voltage shift results collected during the low voltage storage. By applying an additional discharging step after the low voltage storage, the trap energies and spatial distributions are derived. I...

N5 technology node dual-damascene interconnects enabled using multi patterning

We demonstrate an integration approach to enable 16nm half-pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho-Etch (LE3) and tone-inversion. A silicon-verified DOE experiment on a SAQP process suggests a tight process window for core etch and spacer depositions. We also show a novel process flow which enable us to pattern tight-pitch metal-cut (block), and effectively scale the trench CD to 12nm at pitch 32nm. Finally we discuss line resistance and resistivity obtained for the 16nm and 12nm trenches created using 193i integration flow.

Study of electromigration mechanisms in 22nm half-pitch Cu interconnects by 1/f noise measurements

The electromigration (EM) performance of Cu interconnects with different barrier/liner combinations is studied by means of 1/f (or generally known as low-frequency) noise measurements. It is shown that Cu interconnects with a TaN barrier and Co liner have lower EM activation energies for 22nm half-pitch line-widths than Ru based liners. Indeed, interconnects with a 1nm Ru liner (both with TaN and Mn-based barriers) are found to outperform lines with a Co liner in terms of EM reliability. A possible explanation for this is a less defective Cu/Ru interface as compared to Cu/Co.