Kevin Vandersmissen

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.

Void-Free Filling of HAR TSVs Using a Wet Alkaline Cu Seed on CVD Co as a Replacement for PVD Cu Seed

The results of a wet alkaline seed deposition process directly on a thin adhesion promoter film, such as chemical vapor deposition (CVD) Co, are presented. This solution has been successfully used for copper plating on blanket and patterned through-silicon-via (TSVs) wafers covered with either silicon oxide/physical vapor deposition (PVD) Ta/CVD Co or silicon oxide/PVD Ti/CVD Co stacks. Such direct plated films were used as seed layers for subsequent copper plating from an in-house-made acidic Cu bath with model additives poly(ethylene glycol) (PEG), bis(3-sulfopropyl) disulfide (SPS), and Janus Green B (JGB). We report the impact of the directly plated stack composition and thicknesses on the integration of the wet alkaline seed in TSVs with 5 μm width and high aspect ratio (HAR) as high as 8:1. The conformal wet seed layer enables the achievement of a successful void-free filling using an in-house made acidic Cu bath with model additives (SPS, PEG, and JGB).

Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects

Higher performance, higher operation speed and volume shrinkage require high 3D interconnect densities. A way to meet the density specifications is to further increase the A.R. of the TSV interconnection. This requires the integration of highly conformal thin films deposition techniques in TSV flows, particularly for metallization. In this study, seed layer enhancement is applied to regular PVD Cu seed for metalizing TSV of diameter of 2μm and aspect-ratio 15:1. The results reported in this paper open a new path for process integration of high A.R. TSVs and provide a versatile and reliable building block for achieving the high density interconnects required for tomorrows 3D electronics devices.

High frequency scanning acoustic microscopy applied to 3D integrated process: Void detection in Through Silicon Vias

Among the technological developments pushed by the emergence of 3D-ICs, Through Silicon Via (TSV) technology has become a standard element in device processing over the past years. As volume increases, defect detection in the overall TSV formation sequence is becoming a major element of focus nowadays. Robust methods for in-line void detection during TSV processing are therefore needed especially for scaled down dimensions. Within this framework, the current contribution describes the successful application of innovative GHz Scanning Acoustic Microscopy (SAM) to TSV void detection in a via-middle approach.

Cobalt bottom-up contact and via prefill enabling advanced logic and DRAM technologies

This work introduces two new metallization schemes using the electroless deposition (ELD) technique; one based on contact fill and one based on via prefill. One of the key features of the electroless process is its selective deposition, which can be used for bottom-up fill of high aspect ratio features. The feasibility of this Co ELD process is demonstrated on contacts landing on W and vias landing on Cu. Our simulation of the Co via resistance shows that it can serve as alternative to Cu with lower via resistance below 15nm dimension. The results from a planar capacitor study show that there is no degraded reliability in an organo-silicate glass low-k film when Co is in direct contact with this dielectric. Therefore, selective Co ELD process for contact and via prefill has the potential to enable future scaling of advanced logic and DRAM technologies.

High Efficiency Silver-Free Heterojunction Silicon Solar Cell

In this work, we present the results of the replacement of silver screen printing on heterojunction crystalline silicon (c-Si) solar cells with a copper metallization scheme that has the potential to reduce the manufacturing cost while improving their performance. We report for the first time silver-free heterojunction c-Si solar cells on 6-in. wafers. The conversion efficiency reached is a record 22.1% for c-Si technology for this wafer size (Voc = 729 mV, Jsc = 38.3 mA/cm2, FF= 79.1%). The total power generated is more than 5 W for 1-sun illumination, which is a world record. Heat-damp reliability tests show comparable performance for mini-modules fabricated with copper metalized as for conventional silver screen printed heterojunction c-Si solar cells.

Modeling of Via Resistance for Advanced Technology Nodes

We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the Synopsys Raphael tool. For this paper, we consider the case of 16 and 12nm self-aligned vias, which are representative for the 7 and 5nm logic technology nodes, respectively. Process emulations are performed by using the Synopsys Sentaurus Process Explorer tool in order to generate 3-D models of the investigated via structures. Finally, via resistance is extracted through current simulations in Raphael, that is, by taking into account the actual conductive path from the wires into the via. We predict that via resistance could increase by more than a factor of 2 from node to node. We show that chamfered vias can exhibit up to 56% less resistance than standard (87° tapered) vias because of the larger cross section at the via top. For the same reason, via resistance sensitivity to via width variations along the direction of the connecting (i.e. upper) wire is smaller for chamfered vias. As far as via misalignment to the connected (i.e. lower) wire is concerned, we demonstrate that in the range of interest, the induced resistance increase is not severe (e.g. 20% or lower), and in particular, via resistance is not inversely proportional to the contact area between the via and the connected wire. If side contact to the connected wire is enabled upon misalignment, the via resistance increase is further reduced. If vias are fully self-aligned, that is, self-aligned to both connecting and connected wires, the impact of misalignment can be neutralized in a certain range by properly oversizing the via mask in the direction along the connecting wire. Finally, we show that Co via prefill can enable a substantial reduction (up to 45%) of via resistance for chamfered vias, where the bottom barrier surface can be significantly increased when raised to the via top by means of the prefill step.

Through-silicon via technology for three-dimensional integrated circuit manufacturing

Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.

Reliability study on cobalt and ruthenium as alternative metals for advanced interconnects

Cobalt and ruthenium are being proposed to replace copper in BEOL interconnects. Using intrinsic TDDB studies, we show that Co needs a barrier to prevent it from drifting into SiO2, where for Ru no drift into any of the three studied dielectrics is observed. Although our intrinsic EM studies on single damascene lines filled with Co suffered from bondpad delamination and a non-optimized CMP, we could still conclude that the EM-performance is better compared to Cu filled lines, where a much better performance of Ru filled lines is demonstrated (>25x). Via failures on Ru schemes show a >5x higher lifetime compared to Cu schemes.

Demonstration of a cost effective Cu electroless TSV metallization scheme

In this work, we present a cost effective Cu electroless (ELD-Cu) metallization scheme in which through-silicon vias (TSVs), can be scaled towards higher aspect ratios. We successfully integrated 30 nm ELD-Cu on 15 nm Ru in 3×50 μm TSVs on 300 mm wafer scale and found excellent electrical reliability. Cost calculations revealed the major impact of the implementation of the platable Ru liner material on the costs for the deposition and chemical mechanical polishing part of the TSV metallization. In addition, we demonstrated a complete TSV filling for the 3.5 nm ALD-Ru case and investigated different kinds of Cu electrodeposition chemistries and their influence on the presence of micro-voids in the TSVs.