Suheng Chen

SiGe BiCMOS Precision Voltage References for Extreme Temperature Range Electronics

We present the first investigation of the optimal implementation of SiGe BiCMOS precision voltage references for extreme temperature range applications (+120 degC to -180 degC and below). We have developed and fabricated two unique Ge profiles optimized specifically for cryogenic operation, and for the first time compare the impact of Ge profile shape on precision voltage reference performance down to -180 degC. Our best case reference achieves a 28.1 ppm/ degC temperature coefficient over +27 degC to -180 degC, more than adequate for the intended lunar electronics applications

A High-Slew Rate SiGe BiCMOS Operational Amplifier for Operation Down to Deep Cryogenic Temperatures

We investigate, for the first time, the design and implementation of a high-slew rate op-amp in SiGe BiCMOS technology capable of operation across very wide temperature ranges, and down to deep cryogenic temperatures. We achieve the first monolithic op-amp (for any material system) capable of operating reliably down to 4.3 K. Two variants of the SiGe BiCMOS op-amp were implemented using alternative biasing schemes, and the effects of temperature on these biasing schemes, and their impact on the overall op-amp performance, is investigated

Development of robust analog and mixed-signal electronics for extreme environment applications

The Integrated Circuits and Systems Laboratory at the University of Tennessee is currently investigating robust CMOS analog and mixed-signal circuit design techniques for extreme environments. In this paper, we present system level and transistor level extreme environment design techniques and measurement results from several test circuits. The design techniques focus on developing high performance operational transconductance amplifiers (OTAs) and op-amps that can operate over a wide temperature range. The test circuits include a 3.3-V ping-pong op-amp, a 3.3-V rail-to-rail I/O op-amp capable of driving resistive loads, and a temperature stable voltage reference and current reference.

SiGe BiCMOS 12-bit 8-channel low power Wilkinson ADC

A multichannel low power analog-to-digital converter (ADC) designed, fabricated and tested in 0.5-mum Silicon Germanium BiCMOS process is reported. The 12-bit ADC features 8 input channels, each having a 10-Ksps sampling rate and an input voltage range of 1.2 V. The ADC architecture, comprised of a ramp generator, comparators, and a Gray code counter, is discussed along with design details of the primary blocks. Measurement data shows a differential nonlinearity of less than 0.5 LSB and an approximate accuracy of 10 bits.

A SiGe BiCMOS instrumentation channel for extreme environment applications

A instrumentation channel has been designed, implemented and tested in a 0.5-mum SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces a range of external sensors to signal processing circuits. Also, analog sampling has been implemented in the channel using a flying capacitor configuration. Measurement results show the instrumentation channel supports input signals up to 200 Hz.

Radiation response of SiGe BiCMOS mixed-signal circuits intended for emerging lunar applications

The effects of proton irradiation on the performance of key devices and mixed-signal circuits fabricated in a SiGe BiCMOS IC design platform and intended for emerging lunar missions are presented. High-voltage (HV) transistors, SiGe bandgap reference (BGR) circuits, a general-purpose high input impedance operational amplifier (op amp), and a 12-bit digital-to-analog converter (DAC) are investigated. The circuits were designed and implemented in a first-generation SiGe BiCMOS technology and were irradiated with 63 MeV protons. The degradation due to proton fluence in each device and circuit was found to be minor, suggesting that SiGe HBT BiCMOS technology could be a robust platform for building electronic components intended for operation under extreme environments.

A novel four-quadrant analog multiplier using SOI four-gate transistors (G/sup 4/-FETs)

A novel analog multiplier using SOI four-gate transistors (G/sup 4/-FETs) is presented. Thanks to the multiple inputs of the G/sup 4/-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers. Only four G/sup 4/-FETs are needed to build the multiplier core. The circuit is feasible with a standard SOI CMOS process. Two different configurations, both based on the linear modulation of the front-gate threshold voltage by the junction-gates, are presented. This paper addresses the theoretical analysis as well as the preliminary measurement results.

Four-Gate Transistor Voltage-Controlled Negative Differential Resistance Device and Related Circuit Applications

A novel voltage-controlled negative differential resistance device, using complementary SOI four-gate transistors (G4-FETs) is presented. Innovative LC oscillator and Schmitt trigger circuits based on the G4-FET NDR device are experimentally demonstrated

Temperature-compensated reference circuits for SOI

Two novel reference circuits that exploit unique aspects of SOI technology are reported. The first is a voltage reference based on the G/sup 4/-FET, a new four-gate transistor possible only in SOI; which achieves a temperature-compensated output voltage without the use of the standard bandgap architecture. The second is a current reference that uses the zero leakage p-well resistor available in many SOI technologies to achieve a low-level, temperature-stable reference current that exceeds the specifications of bulk CMOS low-level current references reported in the literature. Both reference circuits have been implemented in a standard 3.3-V/0.35-/spl mu/m partially depleted (PD)-SOI process.

Switched capacitor bandgap voltage reference for sub-1-V operation

A switched capacitor bandgap voltage reference circuit capable of sub-1-V operation is presented. The proposed circuit generates a sub-1-V reference voltage with a switched capacitor operation, offering several performance advantages over the current-mode sub-1-V counterpart. The proposed design provides an improved supply rejection and outperforms in the presence of process variation. In addition, the circuit does not require a start-up circuit and the associating trimming circuitry is simplistic and cost effective. The proposed sub-1-V switched capacitor BGR can be a practical sub-1-V reference candidate in ultra deep sub-micron CMOS processes.