Y. Toyoshima

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

A 54 b*54 b multiplier fabricated in a double-metal 0.5 mu m CMOS technology is described. The 54 b*54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz. >

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg = 15 nm and Wfin =15 nm at Vd= 1.0 V and Ioff= 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length

Steep channel profiles in n/pMOS controlled by boron-doped Si:C layers for continual bulk-CMOS scaling

Steep channel impurity-profiles formed by Si∶C+Si epitaxial growth have been extensively studied. Especially in pMOS, several concerns are solved by boron-doping underneath Si∶C layers. Finally, performance improvement realized by steep channel profiles has been demonstrated in both nMOS and pMOS with the same epitaxial channel structure.

Steep channel & Halo profiles utilizing boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond

Si:C layers under non-doped-Si epitaxial channel (Epi-channel) produces steep channel profile for 25 nm-LG nMOSFET. Si:C layers work as the dopant-diffusion-barriers from the boron doped regions. Moreover, retrograde Halo profiles are also realized in this structure. Steep channel profiles at scaled device are confirmed, and the benefits of its profile at LG of 25 nm are discussed.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.

Manufacturable local interconnect technology fully compatible with titanium salicide process

Local interconnect technology has been widely accepted because of advantages such as increase of packing density and reduction of parasitics. Local interconnect technology of a new structure utilizing TiSi/sub 2/ from the reaction of Ti and polysilicon is described. The technology is fully compatible with the salicide process. Moreover, the processing offers low resistivity interconnection with low junction leakage because of its inherent structure. It is confirmed that the process is manufacturable for 0.5 mu m CMOS.<<ETX>>

Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors

Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS) source/drain transistors for the first time. DSS greatly improves propagation delay in multiple fan-in NAND gates at constant standby current. The delay is enhanced to 21% at 0.8V for 3-input NAND gates. Energy delay product (EDP) is improved by more than 50% with DSS at 0.8V

Analysis of hot-carrier-induced degradation mode on pMOSFET's

Hot-carrier-induced degradation surface-channel (p/sup +/ polysilicon gate) and buried-channel (n/sup +/ polysilicon gate) pMOSFETs is discussed. In the shallow gate bias region, a hot-carrier degradation mode by drain avalanche hot hole injection was found for the surface-channel pMOSFETs. Trapped holes and interface state generation, which were not observed in the buried-channel pMOSFETs, were detected. In this gate bias region, the degradation for the surface-channel structure is smaller than that for the buried-channel structure. Three reasons for the smaller degradation in the surface-channel structure are discussed. The deep-gate bias region was also investigated. In this region, an interface-state generation mode without the threshold-voltage shift was found for both surface- and buried-channel pMOSFETs. This interface state generation is caused by channel hot hole injection. >

Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's

The analysis indicates that a thinner gate oxide nMOSFET shows smaller degradation. Mechanisms for the smaller degradation were analyzed using a simple degraded MOSFET model. It was found that the number of the generated interface states is defined uniquely by the amount of peak substrate current, independently from the gate-oxide thickness. The major cause of the smaller degradation in the thinner gate-oxide device is smaller mobility degradation due to the generated interface states. The degraded mobility was measured and formulated. The smaller mobility degradation is explained by the difference between the vertical electric field dependence of the Coulomb scattering term and that of the phonon term under the inversion condition. The effect of a larger channel conductance, due to the larger inversion charges for the thinner gate-oxide device, is the secondary cause for the smaller degradation. >

Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a [111] surface-oriented Si substrate were investigated and compared with those on a [100] substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the [111] substrate is smaller than that on the [100] substrate and that of p-MOSFETs on [111] is larger than that on [100] until the direct-tunneling gate oxide regime. It has been found that most of the electrical properties of MOSFETs, with the notable exception of mobility, become almost identical for [100] and [111] substrates when the oxide thickness is reduced to less than 2.0 nm. Some of the properties are quite different between the two substrates for the thicker oxide case. It has been found that the reliability of hot carrier injection and time-dependent dielectric breakdown (TDDB) of the oxides and MOSFETs on the [111] substrate is slightly better than that on the [100] substrate. In addition, the characteristics and reliability of oxides and MOSFETs on a wafer tilted 4/spl deg/ from [100] axis were investigated. It was found that there are few differences in the mobility between [100] and [100] 4/spl deg/ off substrates for both n- and p-MOSFET cases. The reliability of oxides or MOSFETs on the wafer was identical to that on normal [100] substrate. These results suggest that ultrathin gate oxide MOSFETs on Si surfaces with various orientations are likely to have practical applications. This is good news for possible future new structures of MOSFETs such as vertical or three-dimensional (3-D) MOSFETs.