M. Popovici

Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory

Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are shown. The Ru/STO/Ru stack demonstrates clearly its potential to reach sub-20u2009nm technology nodes for dynamic random access memory. Downscaling of the equivalent oxide thickness, leakage current density (Jg) of the MIMCAPs, and physical thickness of the STO have been realized by control of the Sr/Ti ratio and grain size using a heterogeneous TiO2/STO based nanolaminate stack deposition and a two-step crystallization anneal. Replacement of TiN with Ru as both top and bottom electrodes reduces the amount of electrically active defects and is essential to achieve a low leakage current in the MIM capacitor.

Scalability of plasma enhanced atomic layer deposited ruthenium films for interconnect applications

Ru thin films were deposited by plasma enhanced atomic layer deposition using MethylCyclopentadienylPyrrolylRuthenium (MeCpPy)Ru and N2/NH3 plasma. The growth characteristics have been studied on titanium nitride or tantalum nitride substrates of various thicknesses. On SiO2, a large incubation period has been observed, which can be resolved by the use of a metal nitride layer ofu2009∼u20090.8 nm. The growth characteristics of Ru layers deposited on ultra-thin metal nitride layers are similar to those on thick metal nitride substrates despite the fact that the metal nitride layers are not fully closed. Scaled Ru/metal nitride stacks were deposited in narrow lines down to 25 nm width. Thinning of the metal nitride does not impact the conformality of the Ru layer in the narrow lines. For the thinnest lines the Ru deposited on the side wall showed a more granular structure when compared to the bottom of the trench, which is attributed to the plasma directionality during the deposition process.

Alternative high-k dielectrics for semiconductor applications

Although the next generation high-k gate dielectrics has been defined for the 45nm complementary metal oxide semiconductor technology node, threshold voltage control and equivalent oxide thickness (EOT) scaling remain concerns for future devices. Therefore, the authors explored the effect of incorporating dysprosium in the gate stack. Results suggest that improved EOT-leakage scaling is possible by adding Dy to the interfacial SiO2 layer in a 1:1 ratio or by adding 10% Dy to bulk HfO2. The deposition of a 1nm Dy2O3 cap layer lowered the threshold voltage by ∼250mV. In addition, for future dynamic random access memory capacitor applications, dielectrics with e of 50–130 are projected by the International Technology Roadmap for Semiconductors, unachievable with standard high-k dielectrics. Theoretical modeling can help direct the experimental work needed for extensive screening of alternative dielectrics. Moreover, materials such as perovskites only exhibit a sufficiently high-k value when properly crystall...

High-k Dielectrics and Metal Gates for Future Generation Memory Devices

The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9-30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (> 6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal-insulator-metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values > 50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates.

Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiO<inf>x</inf> interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k dielectric and thin Ru bottom electrode. Record low Jg of 10⁻⁶ A/cm² (10⁻⁸ A/cm²) is achieved for EOT of 0.4 nm (0.5 nm) at 0.8 V. Our data is compared favorably (> 100× Jg reduction at 0.4 nm) to previous best values in literature for MIMcaps with ALD dielectrics.