M. Sherony

A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate

This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-μm SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOMT) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOMT of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is -126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 μW.

A power-efficient 33 GHz 2:1 static frequency divider in 0.12-/spl mu/m SOI CMOS

A 2:1 static frequency divider was fabricated in a 0.12-/spl mu/m SOI CMOS technology. The divider exhibits a maximum operating frequency of 33 GHz. When the power consumption is scaled down to 2.7 mW, a maximum operating frequency of 25 GHz is measured.

High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications

This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 /spl mu/m SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH//spl mu/m/sup 2/ is obtained for a 42 nH MTS (Multi-turn, multiple metal layers in Series) inductor.This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 /spl mu/m SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-Turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH//spl mu/m/sup 2/ is obtained for a 42 nH MTS (Multi-Turn, multiple metal layers in Series) inductor.

Mainstreaming of the SOI technology

Partially-depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. In this paper, the challenges of mainstreaming the SOI technology in device, material, technology and circuit terms are described.Partially-depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. In this paper, the challenges of mainstreaming the SOI technology in device, material, technology and circuit terms are described.

3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.

Suitability of Scaled SOI CMOS for High-Frequency Analog Circuits

In this paper we show that the ability of SOI NMOS transistors to function as high-bandwidth amplifiers continuously improves as gate length shrinks below 50 nm. fT of 196 GHz is achieved at Lpoly = 47 nm. Neither the transconductance nor the input capacitance reaches a limiting value at Lpoly = 47 nm. The gate sheet resistance, which influences the FET input resistance and high-frequency noise, shows little variation and is an acceptable value (7: /square) in the Lpoly = 55 nm to 77 nm range. We also present four features of an aggressively scaled 0.13-Pm partially-depleted SOI CMOS technology that show its suitability for high-frequency circuit applications: RF noise performance comparable to state-of-the art III-V devices, body-tied SOI FETs that achieve the same low-frequency noise as bulk FETs, a multilevel back-end that allows high-density and high-Q passives, and negligible floating-body-induced jitter in RF circuits. 1. FET scaling

Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS

The ultra-thin gate oxide required for the 0.13 /spl mu/m generation and beyond introduces a significant amount of gate-to-body tunneling current. The gate current modulates the body voltage and therefore the history effect. This paper discusses several methods to minimize the impact of gate current, which can cause excessive history effect in 0.10 /spl mu/m SOI CMOS. Our result demonstrates that the combination of high gate leakage and small junction capacitance can enhance circuit performance due to beneficial gate coupling. Ultra-low junction capacitance can be achieved by aggressive SOI thickness scaling, though, the proximity of source/drain extension and channel depletion to the buried oxide complicates device design and modeling.

Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation

The scalability of SOI CMOS technology into the low voltage high performance regime and its comparison with bulk CMOS technology is presented. Based on ring oscillator performance, the 0.13 /spl mu/m SOI CMOS technology can achieve more than 25% faster speed and/or 50% less active power compared to a similar bulk technology.

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power and the inherent low capacitance of densely integrated devices. As shown in this paper, aggressively scaled silicon-on-insulator (SOI) CMOS is a promising technology for SoCs for several reasons: Transistor scaling leads to active power reduction in the sub-50-nm-channel-length regime, standard interconnect supports the high-quality passive devices essential to communications circuitry, and high-speed analog circuits on SOI are state of the art in terms of both performance and power dissipation. We discuss the migration of a complete digital circuit library from bulk to SOI to prove that SOI CMOS supports ASIC-style as well as fully custom circuit design.

A 12dBm 320GHz GBW distributed amplifier in a 0.12/spl mu/m SOI CMOS

This paper describes a 9-stage distributed amplifier which achieves 11 dB gain and 90 GHz 3dB cut-off frequency, equivalent to a 320 GHz GBW. The measured 1 dB output compression point is 12 dBm at 20 GHz, the OIP3 is 15.5 dBm at 50 GHz, and the noise figure is 5.5 dB at 18 GHz.