Mohamed Talbi

A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology. On high resistivity substrate

This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-μm SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOMT) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOMT of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is -126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 μW.

A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology

This paper presents five-stage and seven-stage traveling-wave amplifiers (TWA) in a 0.12-/spl mu/m SOI CMOS technology. The five-stage TWA has a 4-91-GHz bandpass frequency with a gain of 5 dB. The seven-stage TWA has a 5-86-GHz bandpass frequency with a gain of 9 dB. The seven-stage TWA has a measured 18-GHz noise figure, output 1-dB compression point, and output third-order intercept point of 5.5 dB, 10 dBm, and 15.5 dBm, respectively. The power consumption is 90 and 130 mW for the five-stage and seven-stage TWA, respectively, at a voltage power supply of 2.6 V. The chips occupy an area of less than 0.82 and 1 mm for the five-stage and seven-stage TWA, respectively.

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits

Systems-on-chips (SoCs) that combine digital and high-speed communication circuits present new opportunities for power-saving designs. This results from both the large number of system specifications that can be traded off to minimize overall power and the inherent low capacitance of densely integrated devices. As shown in this paper, aggressively scaled silicon-on-insulator (SOI) CMOS is a promising technology for SoCs for several reasons: Transistor scaling leads to active power reduction in the sub-50-nm-channel-length regime, standard interconnect supports the high-quality passive devices essential to communications circuitry, and high-speed analog circuits on SOI are state of the art in terms of both performance and power dissipation. We discuss the migration of a complete digital circuit library from bulk to SOI to prove that SOI CMOS supports ASIC-style as well as fully custom circuit design.

A 12dBm 320GHz GBW distributed amplifier in a 0.12/spl mu/m SOI CMOS

This paper describes a 9-stage distributed amplifier which achieves 11 dB gain and 90 GHz 3dB cut-off frequency, equivalent to a 320 GHz GBW. The measured 1 dB output compression point is 12 dBm at 20 GHz, the OIP3 is 15.5 dBm at 50 GHz, and the noise figure is 5.5 dB at 18 GHz.

A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-/spl mu/m SOI CMOS technology

This paper presents a three-stage CML (current mode logic) ring VCO fabricated in a 0.12 /spl mu/m SOI CMOS technology with a minimum stage delay of 5.4 ps at a differential voltage swing of 400 mV. The maximum oscillation frequency measured is 31 GHz. A tuning range as high as 10% is measured. The phase noise is -95.6 dBc at an offset frequency of 10 MHz. The energy per stage is as low as 26.8 fJ at a power supply voltage of 1.5V and a delay per stage of 5.95 ps.

A 4-91 GHz distributed amplifier in a standard 0.12 /spl mu/m SOI CMOS microprocessor technology

This paper presents five-stage and seven-stage distributed amplifiers (DA) in a 0.12 /spl mu/m SOI CMOS technology. The five-stage DA has a 4 to 91 GHz bandpass frequency with a gain of 5 dB. The seven-stage DA has a 5 to 86 GHz bandpass frequency with a gain of 9 dB. The power consumption is 90 and 130 mW for the 5-stage and 7-stage respectively at a voltage power supply of 2.6 V. The chips occupy an area of less than 0.82 and 1 mm/sup 2/ for the 5-stage and 7-stage respectively.

The effect of OPC optical and resist model parameters on the model accuracy, run time, and stability

Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits manufactured with optical lithography technology. The accuracy of these models highly depends on the experimental data used in the model development and on the appropriate selection of the model parameters. The optical and resist model parameters selected during model build have a significant impact on the OPC model accuracy, run time, and stability. In order to avoid excessively high run times as well as ensure acceptable results, a compromise must be made between OPC run time and model accuracy. The modeling engineer has to optimize the necessary model parameters in order to find a good trade-off that achieves acceptable accuracy with reasonable run time. In this paper, we investigate the effect of some selected optical and resist model parameters on the OPC model accuracy, run time, and stability.

Model-based calculation of weighting in OPC model calibration

Optimal Proximity Correction (OPC) models are calibrated with Scanning Electron Microscope (SEM) data where the measurement uncertainty vary among pattern types (i.e., line versus space, 1D versus 2D and small versus large). The quality of the SEM measurement uncertaintys impact on OPC model integrity is mitigated through a weighting scheme. Statistical methods such as relating the weight to the SEM measurements standard deviation require more measurements per calibration structure than economically feasible. Similarly, the use of experience and engineering judgment requires many iterations before some reasonable weighting scale is determined. In this paper we present the results of OPC model fitness statistics associated with metrology based weights (MtBW) versus model based weights (MBW). The motivation for the latter approach is the promise for an unbiased, consistent, and efficient estimate of the model parameters.

The effect of calibration feature weighting on OPC optical and resist models : investigating the influence on model coefficients and on the overall model fitting

Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits that are manufactured with optical lithography technology. The accuracy of these models depends highly on the experimental data used in the model development (model calibration) process. The calibration features are weighted relative to each other depending on many aspects, this weighting plays an important role in the accuracy of the developed models. In this paper, the effect of the feature weighting on OPC models is studied. Different weighting schemes are introduced and the effect on both the optical and resist models (specifically the resist model coefficients) is presented and compared. The effect of the weighting on the overall model fitting was also investigated.

Highly manufacturable 40-50 GHz VCOs in a 120 nm system-on-chip SOI technology

This paper presents the design optimization and experimental results of 40-50 GHz VCOs for embedded RF integrated circuits that are widely tunable and therefore highly manufacturable. We achieved up to 15% frequency tuning range from 43.5 to 50.5 GHz and -90.2 dBc/Hz phase noise performance at 1 MHz offset from 50.1 GHz operating frequency. The total power dissipation is 15 mW at 1.8 V. The VCOs are fabricated in a 120 nm SOI technology.