Tadahiko Nishimukai

Realization of Gmicro/200

The Gmicro/200, a microprocessor that has been developed as part of Japans TRON (The Real-Time Operating Nucleus) project, is described. This microprogram-based processor with six-state pipeline, 730000 transistors and on-chip caches will serve in an engineering workstation or a high-speed graphics accelerator system. The authors discuss features of the instruction set; memory management; handling of exceptions, interrupts and traps; and the implementation of the Gmicro/200.<<ETX>>

A 1000 MIPS BiCMOS microprocessor with superscalar architecture

A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe circuit techniques of the cache, TLB, register, file, and ALU (arithmetic and logic unit) operating at 250 MHz.<<ETX>>

On-chip multiple superscalar processors with secondary cache memories

The development of an experimental high-performance microprocessor chip based on a 0.3- mu m BiCMOS technology is discussed. It is designed to operate at a 250-MHz clock rate. It includes two processors, each of which executes two instructions in parallel. The chip performs 1000 MIPS when instructions and data are fetched from primary caches. It also includes a four-wave interleaved secondary cache assessed in parallel according to a split-bus protocol, to reduce shared memory conflicts. The VLSI architecture and design results of this chip are described.<<ETX>>

Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor

A stack cache scheme in combination with a general register set is presented as an alternative to the register file. Two cache memories, a 1-K byte code cash and a four-entry cache for branch instructions, are also embedded to accelerate the pipeline stream. This scheme has been implemented and evaluated on a 32-bit microprocessor, the Hitachi H32/200, based on TRON (The Real-time Operating system Nucleus) specifications. This processor contains 730 K transistors in 1.0- mu m CMOS. It performs 6 to 7 MIPS (million instruction per second) at a 20-MHz clock rate.<<ETX>>

Aliasing probabilities and weight distributions of several codes

Signature testing is proposed for integrated circuit testing. One of the problems in signature testing is that not all the errors contained in the test response from the tested circuit can be detected (aliasing error). In this paper, the following results are shown: (1) utilizing the property of the maximum distance separable code, the aliasing probability of the multiple-input signature register (MISR) is formulated. It is shown that the aliasing error probability of the MISR does not depend on the selected polynomial. In addition, it is shown that there is no fluctuation as is observed in the case of single-input linear feedback shift registers (LFSR); (2) the aliasing error of the multiplexed MISR based on the primitive polynomials is analyzed using the weight distribution of the Reed-Solomon codes. It is also shown that there is no fluctuation as is observed in single-input LFRS; (3) the aliasing probability for single-input LFSR is analyzed using a computer program. It is verified that the aliasing probability of single-input LFSRs has different properties depending on the selected primitive polynomial. The fluctuation in the aliasing probability is observed.

Outline of Gmicro/200 and Memory Management Mechanism

This paper outlines the 32-bit microprocessor Gmicro/200 and its memory management mechanism on chip. This microprocessor’s target performance is 6 MIPS. To achieve this performance, a 6-stage pipeline, 5-unit distributed processing, 1-kbyte instruction cache, 128-byte stack cache, and 16-byte branch prediction table are used. The virtual memory management mechanism defined by the memory management unit (MMU) is 2-level paging with dual regions. the translation look-aside buffer (TLB) has 32 entries. It translates logical address within one machine cycle (50 ns) to physical address. The pipeline of the address translation and the external bus access cancels address translation delay.

Hitachi - PA/50, SH Series Microcontroller

Design methodologies for Hitachis RISC microprocessors and microcontrollers are discussed. One of the processors is a high-end PA-RISCTM. The others, the PA/50 and the SH series microcontroller, are low power and low cost processors. Low cost processors require small chip sizeand short design time. To shorten the architecture level design time, we have developed a RT-level behavior simulation tool based on C language. And to reduce the total design time, we use a gate-level synthesis program from the behavior model description. This approach resulted in the low power 42 MIPS/W PA-RISCTM processor (the PA/50, which run at a 33 MHz clock rate) being completed within 15months. Another approach to minimizing chip size while maintaining high performance is to reduce the design turnaround time by using microcode instead of direct wired logic design. We wrote 480-word microcodes equivalent to a 5.8K transistor logic. After assigning the control stages for the microcode fields, we used an in-house logic synthesis and optimized for performance and chip size. The CPU core of the SH series microcontroller occupies only 8 mm2 including CPU core and multiplier circuit. The processor reaches 16 MIPS at 20 MHz. It took 17 man-months to realize a minimum 8 mm2 chip. The total control logic consists of 27 thousand transistors.