Makoto Ohi

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories. >

A 5 volt only 16M bit flash EEPROM cell with a simple stacked gate structure

A 3.6 mu m/sup 2/ 5 V only 16 Mb flash EEPROM cell was obtained using a simple stacked gate structure and a conventional 0.6 mu m CMOS process. A single 5 V power supply operation of the simple stacked gate cell was realized by optimizing the well impurity concentration and the drain structure and using a gate negative biased erasing operation. It is also shown that the gate negative biased erasing operation mode is very effective in improving the cell endurance characteristics.<<ETX>>

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 mu m*2.0 mu m and a chip size of 6.5 mm*18.4 mm were achieved using a simple stacked gate cell structure and 0.6- mu m CMOS process. >

Row-redundancy scheme for high-density flash memory

Flash memory is recognized as one of the key devices of personal digital assistant and other portable equipment. Rapid expansion of the market is expected because it is estimated that the cost of flash memory will eventually be lower than that of DRAM. However, to achieve low cost, a highly efficient redundancy scheme must be implemented for the chip. Although the same column redundancy scheme used in DRAM and SRAM can be applied to flash memory, conventional row redundancy in which defective word lines are replaced by spare word lines is not suitable. In flash memory, all memory cells in the erase block must be programmed before the erase pulse is applied to the memory array to avoid over-erasure. If the replaced word line is shorted to the adjacent word line, memory cells on the defective word line cannot be programmed even if the replaced word line is selected because the word line is grounded through the adjacent word line.<<ETX>>

OPTIMIZATION OF NITRIDATION AND REOXIDATION CONDITIONS FOR AN EEPROM TUNNELING DIELECTRIC

We show that the maximum reoxidation time is one of the useful parameters for determining the optimum processing condition of reoxidized nitrided oxide (RONO) film. The maximum reoxidation time is defined as the time in which the thickness of a nitrided oxide film increases 10%. Since many RONO process parameters have a close relationship to this parameter, it is easy to determine an optimum RONO condition. Using such an optimized condition of RONO film formation, that is, performing the nitridation of oxide in 50% NH3 ambient at 1050°C for 30 s and following it with reoxidation in O2 ambient at 1100°C for 120 s, we formed 9-nm-thick RONO film as the EEPROM tunnel dielectric. The film is found effective not only in improving the endurance to more than 106 cycles, but also in causing no degradation at all to the characteristics of the 1M-bit EEPROM devices actually fabricated.

A High Density High Performance Cell for 4M Bit Full Feature Electrically Erasable/Programmable Read-Only Memory

A new electrically erasable / programmable read-only memory (EEPROM) cell structure is proposed, which achieves a high capacitive coupling ratio of more than 0.8 in a small cell size of 11.25 µm2 using 0.6 µm lithography. This new cell has sufficient cell threshold windows which extend to more than 5 volts and a programmed cell current of more than 30 µA at a program voltage of 14 volts. The cell endurance is more than 105 erase/write cycles. Using this cell structure, a 4-mega-bit full-feature EEPROM of high performance and high reliability can be acquired.