Yuichi Kunori

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V/sub cc/ and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 /spl mu/m, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8/spl times/1.6 /spl mu/m/sup 2/ and the chip measures 5.8/spl times/5.0 mm/sup 2/. The divided bit line structure realizes a small NOR type memory cell. >

New erase scheme for DINOR flash memory enhancing erase/write cycling endurance characteristics

New erase scheme for DINOR (Divided Bit Line NOR) flash memory is proposed and investigated, which utilizes substrate hot electron(SHE) injection instead of FN tunnel injection for erasure. Additional process or alteration of the cell structure is not needed to realize SHE erasure. The cell is formed in a triple well structure. The bottom n-well layer, which surrounds the p-well, is used as electron supply source in the SHE. By adopting SHE for erasure, the electric field required across the tunnel oxide was reduced to 1/4, compared with FN erasure. It needs less than 1 second for erasure, which is sufficient for DINOR operation. It is shown that V th window narrowing during erase/write cycling was significantly reduced by using SHE for erasure, as compared with using FN tunneling. The mechanism of enhanced erase/write cycling endurance is also examined.<<ETX>>