Maksim Gorev

Fault simulation with parallel exact critical path tracing in multiple core environment

A novel fault simulation method is proposed, based on exact critical path tracing beyond the Fan-out-Free Regions (FFR) throughout the full circuit. The method exploits two types of parallelism: bit-level parallelism for multiple pattern reasoning, and distribution the fault reasoning process between different cores in a multi-core processor environment. To increase the speed and accuracy of fault simulation, compared with previous methods, a mixed level fault reasoning approach is developed, were the fan-out re-convergence is handled on the higher FFR network level, and the fault simulation inside of FFRs relies on the gate-level information. To allow a uniform and seamless fault reasoning, Structurally Synthesized BDDs (SSBDD) are used for modeling on both levels. Experimental research demonstrated very promising results in increasing the speed and scalability of the method.

Combinational fault simulation in sequential circuits

We propose a very fast fault simulation method which is based on exact parallel critical path tracing developed for combinational circuits. To convert the sequential problem of fault simulation into the combinational one we introduce into the circuit a set of MISRs to improve the circuits observability. The role of these MISRs is to monitor signals on the global feedback loops, and on selected fan-out stems in the circuit. The given sequential circuit is partitioned into a set of sequential or combinational sub-circuits, with breakpoints at global feedback loops or at selected fan-out stems. The simulated test sequence is mapped into local sets of input patterns applied to the sub-circuits. For these local test patterns, each sub-circuit is fault simulated by exact parallel critical path tracing similarly as a combinational equivalent circuit. The feasibility and correctness of the method is shown, and the experimental results which demonstrate the speed-up achieved by the method are provided.

Reconfigurable data acquisition unit for bioimpedance measurements

Multi-channel data-acquisition devices are used often in biomedicine to measure properties of organs/tissues. A DSP-based solution for a multi-frequency measurement unit has been proposed and implemented. In this paper, extensions to the existing prototype data acquisition unit are discussed. The extensions were designed to allow to reduce the aliasing effect.

Optimization of multisine excitation for a bioimpedance measurement device

Multisine excitation is widely used in impedance measurements to retain the advantages of the sine wave, while reducing the measurement time. To keep the crest factor (CF) of the excitation signal low, the initial phases of the signal components must be optimized. This paper focuses in further optimization of multisine signal for improving the signal-to-noise ratio (SNR) of measurements, reducing the complexity of signal generation and minimizing a memory footprint of the FPGA based implementation.

A benchmark suite for evaluating the efficiency of test tools

We propose a benchmark suite for systematic evaluation of efficiency of new CAD and test algorithms. The suite consists of a set of high performance signal processors. Differently from all other existing benchmark suites, all the member processors of this family perform the same function, but are implemented in different ways, differing mainly in sharing of computing resources. The circuits are characterized by different structural complexities measured in the number of reconvergent fan-outs. The latter feature has the main impact to the testability of circuits, influencing directly on the efficiency of test tools and on the quality of the given test set. The main advantage of the benchmark suite, compared to the existing ones, relies in the possibility to create systematic dependencies of the efficiency of test algorithms or test quality as a function of the structural complexity of circuits.

Implementation of multisine signal generator for a bioimpedance measurement device

Implementing a high-speed multisine-wave synthesiser in hardware is, although common, but hardly a trivial task. In this paper we review an approach and propose the FPGA implementation for generating a multisine signal. The most appropriate method for a given bioimpedance measurement device is improved and implemented.

Comparison of two approaches to improve functional BIST fault coverage

Two approaches to improve the fault coverage of functional logic BIST in digital circuits are proposed and investigated. The first approach is based on introducing of additional test points. An experimental tool set is developed for fast evaluation of the number of control points that is needed to achieve 100% fault coverage for the given functional test sequence. A novel algorithm is proposed to minimize the number of control points. The second approach is based on complementing the functional test with additional deterministic test patterns. The pros and cons of both approaches are highlighted and discussed.

At-speed self-testing of high-performance pipe-lined processing architectures

We propose a new methodology for Built-In Self-Test (BIST) where contrary to the traditional scan-path based logic BIST, the proposed solution for test generation does not need any additional hardware, and will not have any impact on the working performance of the system. A class of digital systems organized as pipe-lined signal processing architectures is targeted. The data used for processing in the system are used as test pattern sources. Testing at normal working conditions, and with typically processed data, allows exercise the system on-line and at-speed, facilitating the detection of dynamic faults like delays and cross-talks to achieve high test quality. The proposed new self-test method is free from the negative aspect of over-testing, compared to the traditional logic BIST approaches, and uses a minimal amount of additional hardware. Experimental research was based on the case study of a specialized bio-signal processor architecture, and the results showed promising results in reducing the cost of testing and achieving high fault coverage.

FPGA based system for video compression and transmission over bluetooth

An implementation of real-time video compression and transmission method using low-cost Field-Programmable Gate Array (FPGA) is presented in this paper. The proposed system utilizes Bluetooth link in order to transmit 88x136 pictures at the rate of up to 17 frames per second. The main focus was on the low-power implementation of the system because of its mobility. This is why the Bluetooth was chosen as wireless carrier. Also the demand for this kind of systems is growing. Therefore the hardware design effort was targeted to the lowest FPGA area usage at the appropriate performance level. This was done by modifying the existing image compression methods in order to simplify the design. The system captures input from widely known CMUCam video camera module and transmits picture to the PC system.

Reprogrammable data acquisition unit to reduce aliasing effect in bioimpedance measurements

Measurement of electrical bioimpedance enables to characterize tissues and organs, to get diagnostic images, etc. A DSP-based solution for the multi-frequency and multi-channel bioimpedance measurement unit has been previously proposed and implemented. Extensions to the existing prototype data acquisition unit are discussed keeping in mind performance and cost requirements while trying to reduce the aliasing effect.