Man Hoi Wong

Threshold Voltage Shift Due to Charge Trapping in Dielectric-Gated AlGaN/GaN High Electron Mobility Transistors Examined in Au-Free Technology

We report on the investigation of the charge trapping characteristics of dielectric-gated AlGaN/GaN high electron mobility transistors (HEMTs) with atomic layer deposited HfO2 (Tetrakis-(ethylmethylamino)hafnium and H2O precursors). The impact of process development and tool contamination in an Au-free 200-mm silicon CMOS line is discussed. The interfacial GaOxNy layer is proposed to be the primary location of long time constant traps. We examine the impact of these trap states on threshold voltage engineering of the gate stack. Enhancement mode operation of HEMTs is demonstrated, and the stability of enhancement mode is discussed.

Benchmarking current density in staggered gap In0.53Ga0.47As/GaAs0.5Sb0.5 heterojunction Esaki tunnel diodes

The impact of dopant concentration on the current densities of In0.53Ga0.47As/GaAs0.5Sb0.5 heterojunction Esaki tunnel diodes is investigated. Increased doping density results in increased peak and Zener current densities. Two different structures were fabricated demonstrating peak current densities of 92 kA/cm2 and 572 kA/cm2, Zener current densities of 994 kA/cm2 and 5.1 MA/cm2 at a −0.5 V bias, and peak-to-valley current ratios of 6.0 and 5.4, respectively. The peak current scaled linearly with area down to a 70 nm diameter. The peak current densities were benchmarked against Esaki diodes from other material systems based on doping density and tunnel barrier height.

Performance Evaluation of In 0.53 Ga 0.47 As Esaki Tunnel Diodes on Silicon and InP Substrates

In_0.53Ga_0.47As Esaki tunnel diodes grown by molecular beam epitaxy on an Si substrate via a graded buffer and control In_0.53Ga_0.47As Esaki tunnel diodes grown on an InP substrate are compared in this paper. Statistics are used as a tool to show peak-to-valley ratio for the III-V on Si sample and the control that perform similarly below 8.6 × 10^-10 cm^-2. The existence of a critical device area suggests the potential to utilize III-V on Si for other deeply scaled tunnel devices.

Characterization of anti-phase boundaries in hetero-epitaxial polar-on-nonpolar semiconductor films by optical second-harmonic generation

Compound semiconductor layers (e.g., GaAs) grown on elemental semiconductor substrates (e.g., Si, Ge) are vulnerable to formation of anti-phase boundary (APB) defects. We show that optical second-harmonic generation (SHG) signals from APB-rich epi-layers are orders of magnitude weaker than from APB-free samples. Moreover, scanning SHG images of APB-rich layers reveal microstructure lacking in APB-free layers. We attribute these findings to the sign reversal of the second-order nonlinear optical susceptibility χijk(2) between neighbouring anti-phase domains within the incident laser spot. In contrast, SHG is insensitive to threading dislocations. Thus, SHG can identify APBs selectively and non-invasively for advanced MOSFET device applications.

Challenges of contact module integration for GaN-based devices in a Si-CMOS environment

The authors report on the integration of an Au-free contact module intended for AlGaN/GaN high-electron-mobility transistors fabricated in a 200 mm Si complementary metal–oxide–semiconductor facility. Contacts are characterized via transfer line method structures, tunneling electron microscopy, and energy-dispersive x-ray spectroscopy. Factors leading to incorrect extraction of contact resistance are discussed. The authors find that reoptimization of chemical vapor deposited silicon nitride on AlGaN/GaN substrates is required to ensure reliable determination of contact resistance, gate-to-source spacing, and gate-to-drain spacing. Additional process development is required to enable parallel processing of Si and GaN devices.

Challenges of III–V materials in advanced CMOS logic

The superior transport properties of III-V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<;60;10nm, N_D=5×10¹⁹ cm^-3, ρ_c= 6Ω.μm² and Dit = 4×10¹² eV^-1 cm^-2. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.