Mitsuhiro Togo

A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs

A new parasitic capacitance reduction technologies, utilizing a Gate-side Air-gap Structure (GAS), has been developed for MOSFETs. The GAS in which a 5-nm-wide air-gap was formed next to the gate reduced the fringe capacitance by half. Hence, the gate delay time was reduced by 4.8 psec at FO=1 and by 16 psec at FO=3 in a 0.25 /spl mu/m CMOS, and power consumption was lowered compared to a conventional structure. We also propose pocket implantation through the GAS to suppress short channel effects with only a slight increase in the junction capacitance.

Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode

We have developed a power-aware CMOS technology featuring variable V/sub DD/ and back-bias control. Three typical operation modes are defined: high-speed mode (V/sub DD/ = 1.2V, V/sub B/ = 0V), nominal mode (V/sub DD/ = 0.9V, V/sub B/ = -0.5V) and power-save mode (V/sub DD/ = 0.6V, V/sub B/ = -2.0V). Compared with nominal mode, one and a half order of magnitude reduction of standby leakage current is achieved with power-save mode, while 75% higher drivability is achieved with high-speed mode. Device reliability for back-bias condition was also investigated. With higher back-bias, NBT (Negative Bias Temperature) degradation for pFET is enhanced especially in the case of thinner gate oxide. From activation energy, we believe the dominant mechanism is SHH (Substrate Hot-Hole) injection. Reduced V/sub DD/ at standby mode drastically alleviates this degradation caused by NBT stress and SHH injection. With appropriate V/sub DD/ and V/sub B/ combination, power-aware 65nm CMOS with sufficient reliability can be achieved.

Low-leakage and highly-reliable 1.5 nm SiON gate-dielectric using radical oxynitridation for sub-0.1 /spl mu/m CMOS

We have developed a low-leakage and highly-reliable 1.5 nm SiON gate-dielectric by using radical oxynitridation. In this development, we introduce a new method for determining ultra-thin SiON gate-dielectric thickness based on the threshold voltage dependence on the substrate bias in MOSFETs. It was found that radical oxidation followed by radical nitridation provides 1.5 nm thick SiON in which leakage current is two orders of magnitude less than that of 1.5 nm thick SiO/sub 2/ without degrading device performance. The 1.5 nm thick SiON was also found to be ten times more reliable than 1.5 nm thick SiO/sub 2/.

Dependence of electrical properties on nitrogen profile in ultrathin oxynitride gate dielectrics formed by using oxygen and nitrogen radicals

We studied nitrogen incorporation in ultrathin oxynitride films by using oxygen and nitrogen radicals, and investigated the dependence of the electrical properties on the nitrogen profile. We found that the nitrogen position in the films could be controlled by using different processing sequences, and that the N concentration could be controlled at values up to 16%. In this process, the interface roughness depends on nitrogen position and nitrogen concentration: the interface roughness tends to increase as the N position close to the SiO2–Si interface and increase with N concentration. The results of an analysis of the electrical properties of these oxynitride films indicated that the best way to form the film was by radical nitridation after radical oxidation. These results show that the nitrogen position should be kept away from the SiO2–Si interface and nitrogen amount should be localized at the surface. Using this process, we have successfully achieved a low-leakage 1.5 nm oxynitride (equivalent oxide...

A robust 65-nm node CMOS technology for wide-range Vdd operation

We have developed a highly reliable 65 nm node CMOS technology, enabling a wide-range of Vdd operation, including overdrive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized an oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled SiN layer process, and an offset-spacer process in order to improve the drive-current at low voltage operation and reliability at high voltage operation. The obtained drive-currents are 730/310 /spl mu/A//spl mu/m with an off-current of 80 nA//spl mu/m at a standard supply voltage of 0.9 V, and 1150/550 /spl mu/A//spl mu/m with an off-current of 180 nA//spl mu/m at an overdrive voltage of 1.2 V, while satisfying strict criteria for transistor reliability.

High performance CMOS for GHz communication IC

A 0.35 /spl mu/m design rule except for gate length was applied to CMOS ICs for giga hertz, low-power operation. To obtain such high speed switching, the gate was reduced to 0.15 /spl mu/m and parasitic capacitance was greatly reduced by a localized channel implant. Using this design technique, a 1:8 DEMUX for optical communication was developed, and has achieved high speed, low-power operation of 2.8 GHz/220 mW (@V/sub DD/=2 V) and 2.6 GHz/37 mW (@V/sub DD/=1 V). This technique was shown to be most effective in fields that require speeds greater than about 1 GHz but do not necessarily require large scale integration.

Electrical properties of 1.5-nm SiON gate-dielectric using radical oxygen and radical nitrogen

We have developed a low-leakage and highly reliable 1.5-nm SiON gate-dielectric by using radical oxygen and nitrogen. In this development, we introduce a new method for determining an ultrathin SiON gate-dielectric thickness based on the threshold voltage dependence on the substrate bias in MOSFETs. It was found that oxidation using radical oxygen followed by nitridation using radical nitrogen provides the 1.5-nm (oxide equivalent thickness) SiON, in which leakage current is two orders of magnitude less than that of 1.5-nm SiO/sub 2/ without degrading device performance in NMOSFETs. The 1.5-nm (oxide equivalent thickness) SiON was also found to be ten times more reliable than 1.5-nm SiO/sub 2/.

Controlling base-SiO/sub 2/ density of low-leakage 1.6 nm gate-SiON for high-performance and highly reliable n/pFETs

We report the importance of high-density base-SiO/sub 2/ for nitridation, and demonstrate a low-leakage and highly reliable 1.6 nm gate-SiON without performance degradation in n/pFETs using a radical process. It was found that the high-density 1.6 nm SiO/sub 2/ is ten times more reliable than low-density SiO/sub 2/ in n/pFETs and is suitable as a base layer for radical nitridation as it maintains the surface nitridation of the SiO/sub 2/ and the ideal SiON/Si-substrate interface. The 1.6 nm SiON with the high-density base-SiO/sub 2/ produces comparable drivability in n/pFETs, and has one and half orders of magnitude less gate leakage in nFETs, one order of magnitude less gate leakage in pFETs, and ten times more reliability in n/pFETs than the 1.6 nm SiO/sub 2/.

High-frequency characteristics and its dependence on parasitic components in 0.1 /spl mu/m Si-MOSFETs

High-frequency characteristics of 0.1 /spl mu/m Si-MOSFETs are evaluated and the influence of parasitic components on f/sub MAX/ are analyzed. It was found that reductions of both the gate resistance and junction capacitance are essential to achieve high microwave performance. By using a tungsten polycide electrode and a local channel implant technique, a f/sub T/ value of 63 GHz for NMOS and 33 GHz for PMOS were obtained with 0.12 /spl mu/m CMOS. f/sub MAX/>f/sub T/ condition was satisfied for L>0.15 /spl mu/m. When a lower resistivity gate electrode, such as titanium silicide, is adopted, f/sub MAX/>f/sub T/ can be easily obtained in 0.1 /spl mu/m CMOS. These results demonstrate that 0.1 /spl mu/m CMOS will be a good candidate for future high-performance and low-cost microwave LSIs.

Oxynitridation using radical-oxygen and -nitrogen for high-performance and highly reliable n/pFETs

We report the importance of oxynitridation using radical-oxygen and -nitrogen to form a low-leakage and highly reliable 1.6-nm SiON gate-dielectric without performance degradation in n/pFETs. It was found that oxidation using radical-oxygen forms high-density 1.6-nm SiO/sub 2/, which is ten times more reliable than low-density SiO/sub 2/ formed by oxygen-ions in n/pFETs and is suitable for the base layer of nitridation. Nitrifying SiO/sub 2/ using radical-nitrogen facilitates surface nitridation of SiO/sub 2/, maintains an ideal SiON-Si substrate interface, and reduces the gate leakage current. The 1.6-nm SiON formed by radical-oxygen and -nitrogen produces comparable drivability in n/pFETs, has one and half orders of magnitude less gate leakage in nFETs, one order of magnitude less gate leakage in pFETs, and is ten times more reliable in n/pFETs than 1.6-nm SiO/sub 2/ formed by radical-oxygen.