Mark Porter

Application of RADSAFE to Model the Single Event Upset Response of a 0.25

The RADSAFE simulation framework is described and applied to model SEU in a 0.25 mum CMOS 4 Mbit SRAM. For this circuit, the RADSAFE approach produces trends similar to those expected from classical rectangular parallelepiped models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit.

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A combination of commercial simulation tools and custom applications utilizing Geant4 physics libraries is used to analyze thermal neutron induced soft error rates in a commercial bulk CMOS SRAM. Detailed descriptions of the sensitive regions based upon technology in computer-aided design calibration are used in conjunction with a physics-based Monte Carlo simulator to predict neutron soft error cross sections that are in good agreement with experimental results

m CMOS SRAM

In this work, heavy ion and energetic proton single event upset (SEU) cross sections are measured for a 4 Mbit CMOS, static random access memory (SRAM). Heavy ion upset cross sections were used to define a dosimetry model suitable for use in a Monte-Carlo, physics-based transport code, which is shown to be predictive for experimentally measured proton single event upset (SEU) cross sections. The simulator was used to quantify the difference between neutron and proton SEU cross sections and to evaluate the fidelity of currently established rate prediction methods. Simulations indicate that established test methods under-predict the FIT rate between 26- 35% for this technology.

Predicting Thermal Neutron-Induced Soft Errors in Static Memories Using TCAD and Physics-Based Monte Carlo Simulation Tools

Implantable medical devices continue to grow in complexity, mirroring the ascent of the semiconductor industry along the Moorepsilas Law curve. Traditionally, implantable applications have taken a fast-follower approach to silicon adoption, using more mature technologies to reduce risk. While commercial manufacturers, in some circumstances, may be able to trade off lifetime requirements for performance, this is decidedly not the case for implantable use, where 10 to 12 year requirements are typical. On the other hand, hardware and software redundancy solutions employed by high reliability avionics, telecommunications, and servers are difficult to implement in a battery-powered device, where current drain restrictions are severe. This paper discusses some of the reliability challenges faced by implantable device manufacturers as the need to provide more sophisticated therapy and diagnostics requires increasingly advanced technologies.

Predicting neutron induced soft error rates: Evaluation of accelerated ground based test methods

As the expectations of physicians and patients have matured, the desire to utilize advanced CMOS technologies to provide increasingly sophisticated therapeutic and diagnostic capabilities has grown. This has pushed the high reliability implantable device business into the use of processes that are much more susceptible to soft error events than in the past. This paper discusses experimental and modeling results of logic upsets in a 0.25 mum CMOS IC process.

Reliability considerations for implantable medical ICs

Experimental thermal neutron and alpha soft error test results of a 4 Mbit SRAM fabricated on a 0.25 mum process are evaluated using Vanderbilt Universitys RADSAFE toolkit. The capabilities of the radiation transport code are demonstrated by accurately reproducing experimental results and predicting operational soft error rates for the memory.