Titash Rakshit

Analysis of graphene nanoribbons as a channel material for field-effect transistors

Electronic properties of graphene (carbon) nanoribbons are studied and compared to those of carbon nanotubes. The nanoribbons are found to have qualitatively similar electron band structure which depends on chirality but with a significantly narrower band gap. The low- and high-field mobilities of the nanoribbons are evaluated and found to be higher than those of carbon nanotubes for the same unit cell but lower at matched band gap or carrier concentration. Due to the inverse relationship between mobility and band gap, it is concluded that graphene nanoribbons operated as field-effect transistors must have band gaps <0.5eV to achieve mobilities significantly higher than those of silicon and thus may be better suited for low power applications.

High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications

This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230 cm2/V-s. The shortest 40 nm gate length (LG) transistors achieve peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V. These represent the highest Gm and fT ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.

Heterogeneous integration of enhancement mode in 0.7 ga 0.3 as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications

This paper describes for the first time, the heterogeneous integration of In0.7Ga0.3As quantum well device structure on Si substrate through a novel, thin composite metamorphic buffer architecture with the total composite buffer thickness successfully scaled down to 1.mum, resulting in high- performance short-channel enhancement-mode In0.7Ga0.3As QWFETs on Si substrate for future high-speed digital logic applications at low supply voltage such as 0.5 V.

Effects of Surface Orientation on the Performance of Idealized III–V Thin-Body Ballistic n-MOSFETs

Ballistic on-currents of thin-body n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) are compared across group IV (Si, Ge) and III-V (InAs, In0.5Ga0.5As, GaAs, GaSb) materials for different body thickness values, surface orientations, and transport directions under several idealization assumptions. Previous simulation studies have shown that, as oxide capacitance increases, typical III-V channels with (100) surface perform worse than Si in the ballistic limit due to the degraded density-of-states (DOS). In this letter, simulation results based on tight-binding band structure calculations verify a recent proposal that confined III-V n-MOSFETs with small Γ-L separations overcome the DOS bottleneck and deliver high injection velocities, boosting on-current performance. By using the quantized L-valleys, GaSb with (100) or (111) surface orientations shows the best ballistic performance, outperforming all other materials. Although GaAs (100) and InAs or In0.5Ga0.5As with any surface orientation suffer from the DOS bottleneck, GaAs (111) gives higher ballistic on -currents than Si does.

Capacitance Compact Model for Ultrathin Low-Electron-Effective-Mass Materials

We present a compact model to calculate the capacitance of undoped high-mobility low-density-of-states materials in double-gate device architecture. Analytical equations for estimating the subband energies, while taking the effect of wavefunction penetration into the gate oxide and the effective mass discontinuity, are presented for the first time in a compact modeling framework. The surface potential equation for a two subband system is solved, assuming Fermi-Dirac statistics, and compared to numerical Schrodinger-Poisson simulations. The importance of accurately treating the charge profile distribution is illustrated, and an analytical expression for the effective oxide thickness to model the charge centroid is developed.

Logic performance evaluation and transport physics of Schottky-gate III–V compound semiconductor quantum well field effect transistors for power supply voltages (V CC ) ranging from 0.5v to 1.0v

In this paper for the first time, the logic performance of Schottky-gate In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFETs is measured and evaluated against that of advanced Strained Si MOSFETs from Vcc = 0.5 to 1.0V. The QWFET is shown to have measured drive current gain over the Si MOSFET for the entire Vcc range. Effective velocity (V<inf>eff</inf>) of the QWFET exhibits 4.6X–3.3X gain over the Si MOSFET. The high V<inf>eff</inf> enables 65% intrinsic drive current gain at V<inf>CC</inf> = 0.5V and 20% gain at V<inf>CC</inf> = 1.0V for the In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFET over that of Strained Si, despite 2.5x lower charge density.

Carbon Nanoribbons: An Alternative to Carbon Nanotubes

The electronic and vibrational properties of carbon nanoribbons (CNRs) are analyzed and compared to carbon nanotubes (CNTs). Transport properties are analyzed from the perspective of use in an FET device. The required sizing and consequent processing requirements are discussed. The overall properties of the CNRs and CNTs are found to be similar, with the primary difference being the more restrictive size vs. bandgap behavior of the CNRs

Device Simulation for Future Technologies

Simulation approaches used in Intel to evaluate the applicability of new devices and materials for future microprocessor technologies are reviewed. Examples discussed include the evaluation of highly stressed materials, III -V HEMT devices, and carbon nanoribbons. The techniques employed are similar to those used in the research community, but focused on efficient evaluation within a versatile infrastructure that works for both development and research.