Rwik Sengupta

Multiple channel length finFETs with same physical gate length

Integrated Circuits with Si and Non-Si Nanosheet FET Co-Integration with Low Band-to-Band Tunneling and Methods of Fabricating the Same

NANOSHEET FETS WITH STACKED NANOSHEETS HAVING SMALLER HORIZONTAL SPACING THAN VERTICAL SPACING FOR LARGE EFFECTIVE WIDTH

METHODS OF FORMING DEFECT-FREE SRB ONTO LATTICE-MISMATCHED SUBSTRATES AND DEFECT-FREE FINS ON INSULATORS

SEMICONDUCTOR DEVICE WITH AN ISOLATION GATE AND METHOD OF FORMING

MULTIPLE CPP FOR INCREASED SOURCE/DRAIN AREA FOR FETS INCLUDING IN A CRITICAL SPEED PATH

SEMICONDUCTOR DEVICE INCLUDING A REPEATER/BUFFER AT HIGHER METAL ROUTING LAYERS AND METHODS OF MANUFACTURING THE SAME

Semiconductor devices including finfets and local interconnect layers and methods of fabricating the same

FLIP-FLOP LAYOUT ARCHITECTURE IMPLEMENTATION FOR SEMICONDUCTOR DEVICE

METAL OXYSILICATE DIFFUSION BARRIERS FOR DAMASCENE METALLIZATION WITH LOW RC DELAYS AND METHODS FOR FORMING THE SAME