Mark Skokan

Bonding for 3-D Integration of Heterogeneous Technologies and Materials

Modern electronic applications demand more and more complex, multifunctional microsystems with performance characteristics which can only be achieved by using best-of-breed materials and device technologies. Three-dimensional (3-D) integration of separate, individually complete device layers provides a way to build complex heterogeneous microsystems without compromising the system performance and fabrication yield. In the 3-D integration approach, each device layer is fabricated separately using optimized materials and processes. The layers are bonded and interconnected through area array vertical interconnects with lengths on the order of microns. This paper will review bonding techniques for high density area array 3-D integration of integrated circuits, focusing on techniques suitable for die-to-die and die-to-wafer bonding configurations.

HDVIP five-micron pitch HgCdTe focal plane arrays

Infrared detector pixel pitch has been decreasing, driven by interest in higher resolution, larger displays, and decreased cost. Previous generations of focal plane arrays (FPAs) were on 50, 40, 30, and 20μm pitch. 12μm pitch FPAs are now available. DRS Network and Imaging Systems has developed ultra-small 5μm pitch infrared detectors for the long-wave infrared (LWIR) and medium-wave infrared (MWIR) bands as part of the DARPA AWARE Lambda Scale effort. The smaller pitch was achieved using DRS’ high-density vertically integrated photodiode (HDVIP®) architecture. This technology is a major advance in the state of the art for infrared imaging sensors. The pixel density of 4 million pixels/cm2 enables the production of lower cost FPAs from HDTV resolution up to many millions of pixels. Dark current, collection efficiency, cross-talk, and operability are similar to larger pitch HDVIP FPAs.

Advanced 3D mixed-signal processor for infrared focal plane arrays: Fabrication and test

We report successful implementation of high-density 3D integration technology in the fabrication of advanced mixed-signal processors for infrared focal plane arrays. Separate analog and digital integrated circuits (ICs) were custom designed and fabricated in standard bulk CMOS technology in two different commercial foundries. The 3D interconnects were arrayed in a 256×256 format with a 30 micron pitch and had the form of through-silicon vias 4 micron in diameter and 30 micron deep. Completed 3D readout IC stacks were tested pixel by pixel, demonstrating operability of 99.9%. The 3D IC stacks were hybridized with infrared photodiode arrays and produced functional FPA imagers with 99.9% array operability and unprecedented performance. Such imaging arrays and other smart sensors enabled by 3D integration of sensing elements with sophisticated signal processing are of increasing interest for Internet-of-Things applications, from net-enabled surveillance to mobile health.

Enabling more capability within smaller pixels: advanced wafer-level process technologies for integration of focal plane arrays with readout electronics

Over the past decade, the development of infrared focal plane arrays (FPAs) has seen two trends: decreasing of the pixel size and increasing of signal-processing capability at the device level. Enabling more capability within smaller pixels can be achieved through the use of advanced wafer-level processes for the integration of FPAs with silicon (Si) readout integrated circuits (ROICs). In this paper, we review the development of these wafer-level integration technologies, highlighting approaches in which the infrared sensor is integrated with three-dimensional ROIC stacks composed of multiple layers of Si circuitry interconnected using metal-filled through-silicon vias.

Linear mode photon counting from visible to MWIR with HgCdTe avalanche photodiode focal plane arrays

Results of characterization data on linear mode photon counting (LMPC) HgCdTe electron-initiated avalanche photodiode (e-APD)focal plane arrays (FPA) are presented that reveal an improved understanding and the growing maturity of the technology. The first successful 2x8 LMPC FPA was fabricated in 2010 [1]. Since then a process validation lot of 2x8 arrays was fabricated. Five arrays from this lot were characterized that replicated the previous 2x8 LMPC array performance. In addition, it was unambiguously verified that readout integrated circuit (ROIC) glow was responsible for most of the false event rate (FER) of the 2010 array. The application of a single layer metal blocking layer between the ROIC and the detector array and optimization of the ROIC biases reduced the FER by an order of magnitude. Photon detection efficiencies (PDEs) of greater than 50% were routinely demonstrated across 5 arrays, with one array reaching a PDE of 70%. High resolution pixel-surface spot scans were performed and the junction diameters of the diodes were measured. The junction diameter was decreased from 31 μm to 25 μm resulting in a 2x increase in E-APD gain from 470 on the 2010 array to 1100 on one of the 2013 FPAs. Mean single photon signal to noise ratios of >12 were demonstrated at excess noise factors of 1.2-1.3. NASA Goddard Space Flight Center (GSFC) performed measurements on the delivered FPA that verified the PDE and FER data.

Performance and modeling of the MWIR HgCdTe electron avalanche photodiode

The operation of the mid-wave infrared (MWIR) HgCdTe cylindrical electron injection avalanche photodiode (e-APD) is described. The measured gain and excess noise factor are related to the to the collection region fill factor. A 2D diffusion model calculates the time dependent response and steady state pixel point spread function for cylindrical diodes, and predicts bandwidths near 1 GHz for small geometries. A 2 μm diameter spot scan system was developed for point spread function and crosstalk measurements at 80 K. An electron diffusion length of 13.4 μm was extracted from spot scan data. Bandwidth data are shown that indicate bandwidths in excess of 300 MHz for small unit cells geometries. Dark current data, at high gain levels, indicate an effective gain normalized dark density count as low as 1000 counts per μs per cm2 at an APD gain of 444. A junction doping profile was determined from capacitance-voltage data. Spectral response data shows a gain independent characteristic.

High operating temperature MCT discrete detector data and analysis

High Density Vertically Integrated Photodiodes (HDVIP) MWIR detectors were fabricated in LPE-grown Mercury Cadmium Telluride material. Devices were fabricated with two different acceptor level concentrations. The low doped n-region was held at a single concentration but the dimensions are tailored to simultaneously maintain high quantum efficiency while minimizing dark current and 1/f noise. Since this study target was for operating at high temperatures, detector I-V data was collected between 120 K and 280 K for I-Vs and 180 to 280 K for noise to understand current mechanisms that limit device performance at these elevated temperatures. Noise as a function of frequency has also been collected over the same temperature range. 1/f noise has also been modeled for MWIR detectors as a function of temperature and will be covered.

Advances in three-dimensional integration technologies in support of infrared focal plane arrays

Staring infrared focal plane arrays (FPAs) require pixel-level, three-dimensional (3D) integration with silicon readout integrated circuits (ROICs) that provide detector bias, integrate detector current, and may further process the signals. There is an increased interest in ROIC technology as a result of two trends in the evolution of infrared FPAs. The first trend involves decreasing the FPA pixel size, which leads to the increased information content within the same FPA die size. The second trend involves the desire to enhance signal processing capability at the FPA level, which opens the door to the detector behaving like a smart peripheral rather than a passive component—with complex signal processing functions being executed on, rather than off, the FPA chip. In this paper, we review recent advances in 3D integration process technologies that support these key trends in the development of infrared FPAs. Specifically, we discuss approaches in which the infrared sensor is integrated with 3D ROIC stacks composed of multiple layers of silicon circuitry interconnected using metal-filled through-silicon vias. We describe the continued development of the 3D integration technology and summarize key demonstrations that show its viability for pixels as small as 5 microns.