Sunit Tyagi

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57/spl mu/m/sup 2/. Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

Summary form only given. We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1 A/cm/sup 2/ for gate leakage is overly pessimistic and that leakage values of up to 100 A/cm/sup 2/ are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50 nm L/sub GATE/ dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50 nm L/sub GATE/ transistors are described for the first time.

In search of "Forever," continued transistor scaling one new material at a time

This work looks at past, present, and future material changes for the metal-oxide-semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moores law, new materials and structures are required. The first major material change to extend Moores law is the use of SiGe at the 90-nm technology generation to incorporate significant levels of strain into the Si channel for 20%-50% mobility enhancement. For the next several logic technologies, MOSFETs will improve though higher levels of uniaxial process stress. After that, new materials that address MOSFET poly-Si gate depletion, gate thickness scaling, and alternate device structures (FinFET, tri-gate, or carbon nanotube) are possible technology directions. Which of these options are implemented depends on the magnitude of the performance benefit versus manufacturing complexity and cost. Finally, for future material changes targeted toward enhanced transistor performance, there are three key points: 1) performance enhancement options need to be scalable to future technology nodes; 2) new transistor features or structures that are not additive with current enhancement concepts may not be viable; and 3) improving external resistance appears more important than new channel materials (like carbon nanotubes) since the ratio of external to channel resistance is approaching /spl sim/1 in nanoscale planar MOSFETs.

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA//spl mu/m and 0.5 mA//spl mu/m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA//spl mu/m and 0.6 mA//spl mu/m respectively. Technology design rules allow a 6-T SRAM cell with an area of 2.45 /spl mu/m/sup 2/, while array specific design rule give the densest SRAM reported to date, the 6-T cell has an area of only 2.09 /spl mu/m/sup 2/. Excellent yield and performance is demonstrated on a 18 Mbit CMOS SRAM.

A high performance 180 nm generation logic technology

A 180 nm generation logic technology has been developed with high performance 140 nm L/sub GATE/ transistors, six layers of aluminum interconnects and low-/spl epsi/ SiOF dielectrics. The transistors are optimized for a reduced 1.3-1.5 V operation to provide high performance and low power. The interconnects feature high aspect ratio metal lines for low resistance and fluorine doped SiO/sub 2/ inter-level dielectrics for reduced capacitance. 16 Mbit SRAMs with a 5.59 /spl mu/m/sup 2/ 6-T cell size have been built on this technology as a yield and reliability test vehicle.

100 nm gate length high performance/low power CMOS transistor structure

We report a very high performance 100 nm gate length CMOS transistor structure operating at 1.2-1.5 V. These transistors are incorporated in a 180 nm logic technology generation. Various process enhancements are incorporated to significantly improve transistor current drive capability relative to the results published by Yang et al. (1998). Unique transistor features responsible for achieving high performance are described. NMOS and PMOS devices demonstrate drive current of 1.04 mA//spl mu/m and 0.46 mA//spl mu/m respectively at 1.5 V and 3 nA//spl mu/m I/sub OFF/. These are the best drive currents reported to date at fixed I/sub OFF/. They represents 10% drive current improvement for both NMOS and PMOS devices relative to the results published by Yang without any change in gate-oxide thickness. High performance is demonstrated down to 1.2 V. Inverter delay of less than 10 psec is reported at 1.5 V at very moderate I/sub OFF/ values.

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

A leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation has previously been presented (Tyagi et al., 2000). In this work, we enhance the previous technology with the following: transistor improvements which support a 60 nm gate dimension and increased drive current, improved 6-T SRAM device matching to allow low power and high performance operation from 0.7 to 1.4 V, and a 5% linear shrink to reduce the 6-T SRAM cell to 2.00 /spl mu/m/sup 2/ while still using 248 nm lithography. Saturation drive currents of 1.30 mA//spl mu/m for N-channel and 0.66 mA//spl mu/m for P-channel low VT devices are the highest reported to date. Excellent device short channel effects are obtained for the 60 nm gate length devices as measured by the 270 mV threshold voltage and <100 mV/V DIBL. These results have been achieved on both 200 and 300 mm wafers.

Source/drain extension scaling for 0.1 /spl mu/m and below channel length MOSFETs

In this paper, we investigate the scaling of source/drain extension (SDE) depth and SDE to gate overlap for 0.1 /spl mu/m and below MOSFETs. We show for the first time that a minimum SDE to gate overlap of 15-20 nm is needed to prevent drive current (I/sub DSAT/) degradation. We also show for the first time that scaling SDE vertical depths below 30-40 nm results in little to no performance benefit for 0.1 /spl mu/m devices and beyond since any improvement in short channel effects due to reduced charge sharing is offset by a large increase in external resistance and poor gate coupling between the channel and extensions.