Martin Dr. Gutsche

A comparative study of dielectric relaxation losses in alternative dielectrics

This work is intended to draw attention to the effect of dielectric relaxation which is shown to severely influence the performance of alternative dielectrics in DRAM storage capacitors as well as of the gate dielectrics of MOSFETs. A comparison of the dielectric relaxation losses in standard insulators with those in most proposed high K dielectrics is presented.

Capacitance enhancement techniques for sub-100 nm trench DRAMs

Essential techniques that allow further scaling of trench DRAMs beyond 100 nm have been developed. Al/sub 2/O/sub 3/ was implemented as a high-k node dielectric in silicon-insulator-silicon trench capacitors. Al/sub 2/O/sub 3/ films were deposited by ALD with excellent step coverage at aspect ratios of up to AR/spl ap/60. Even after thermal stressing at 1050/spl deg/C an effective oxide thickness (=capacitance equivalent thickness) of t/sub ox/=3.6 nm and a leakage current of well below 1 fA/cell were obtained. Both selective and non-selective HSG Si was formed inside high-aspect ratio straight and bottled trenches. On fully integrated 0.17 /spl mu/m trench DRAMs, a storage capacitance of 45 fF/cell with acceptable leakage current was achieved. Both the aluminum oxide node dielectric and the HSG silicon have thus been proven to withstand the high thermal budget required for integration into trench DRAMs. In addition, a silicon etch process was developed that allows trench aspect ratios of AR/spl ap/60 at critical dimensions of CD=80 nm.

A fully integrated Al 2 O 3 trench capacitor DRAM for sub-100 nm technology

For the first time, fully integrated 128 Mb trench DRAMs using Al/sub 2/O/sub 3/ as high-k node dielectric in silicon-insulator-silicon (SIS) capacitors were successfully fabricated. A highly manufacturable integration scheme for Al/sub 2/O/sub 3/ as node dielectric in trench capacitors was developed and successfully implemented in a 170 nm ground rule technology. A capacitance close to 50 fF/cell with leakage current well below 1 fA/cell was achieved, leading to significantly improved retention characteristics. 128 Mb DRAM devices with full functionality and excellent test yields were obtained. The scalability of this technology to smaller dimensions is demonstrated by the integration of ALD (Atomic Layer Deposition) Al/sub 2/O/sub 3/ into 110 nm ground rule trench capacitors. In addition, trench capacitors with Al/sub 2/O/sub 3/ on hemispherical grain (HSG) silicon were fabricated, exhibiting high capacitance enhancement with low leakage current.