Georg Röhrer

Investigations on the high current behavior of lateral diffused high-voltage transistors

This paper describes the high current behavior of a lateral, n-channel, high-voltage transistor. The starting points are TCAD experiments where the phenomenological behavior is analyzed. Based on these results a transistor high current model is derived, which is based on the vertical integrated free carrier concentration in the drift region. The important model parameter is the gate voltage, which defines the boundary condition for the free electron concentration at the beginning of the drift region. Because of the coupling of the carrier continuity equation and the Poisson equation (drift-diffusion model), this boundary condition plays a major role, and defines the carrier concentration inside the drift region. Together with an intrinsic low-voltage transistor model (intrinsic NMOS transistor), a series network is solved numerically. The network behavior reflects the TCAD experiments quite well and covers the different electrical regimes (the on-resistance regime, the quasi-saturation regime, and the saturation regime). The model output is compared with the TCAD experiments and the measured transistor data as well.

Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors

With the continuing scaling of metal–oxide–semiconductor (MOS) devices, the hot-carrier (HC)-induced device degradation has become a major reliabiliy concern in sub- and deep-submicrometre MOS field-effect transistors (MOSFETs) and lateral double-diffused MOSFETs (LDMOSFETs). It is believed that the degradation is mainly due to the effects of the generated oxide-trapped charges and interface traps at the Si/SiO2 interface. In general, the large electric field is strongly localised in a well-defined region; therefore carrier injection and interface-trap creation are similarly concentrated. The strongly inharmonious characters of HC injection and resulting damage present a considerable challenge to both experimental and modelling efforts.The HC degradation behaviour of an n-channel LDMOS transistor is investigated under various stress conditions. By applying variable base charge pumping experiments, a consistent picture of the degradation mechanism can be depicted. HC-induced interface traps are generated in the channel region of the device, in the drift region below the thick field oxide and at the birds beak edge. The latter is shown to dominate the degradation of Idlin, which is the most critical parameter concerning HC lifetime in this specific device.