Verena Vescoli

FlexRay Transceiver in a 0.35µm CMOS High-Voltage Technology

This paper presents one of the first fully functional FlexRay transceivers manufactured in a 0.35 mum CMOS high-voltage technology, which provides high voltage MOS devices together with standard 3.3 V gates. The circuit operates as interface between a generic controller and the copper wire FlexRay physical bus, to be used in fault tolerant and fail safe applications. In particular, the transceiver meets the operating requirements of the automotive environment. The design was validated by means of simulations and experimental measurements on fabricated prototypes

Investigations on an Isolated Lateral High-Voltage n-channel LDMOS Transistor with a Typical Breakdown of 150V

This work describes a concept of an isolated high-voltage (HV) n-channel LDMOS transistor, which can be used as a high-side switch instead of a HV PMOS transistor. HV n-channel LDMOSFETs for 120V applications (blocking voltage over 150V) were used in the study. The devices were fabricated in a 0.35 mum CMOS-based HV technology. Hot carrier stress experiments (under gate voltage VGS = 10V and drain voltage VD = 120V) were performed for device reliability evaluations. The devices with non-uniformly optimized n-well show an excellent trade-off between blocking voltage (BV) and on-resistance while keeping hot carrier induced degradation low

Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors

With the continuing scaling of metal–oxide–semiconductor (MOS) devices, the hot-carrier (HC)-induced device degradation has become a major reliabiliy concern in sub- and deep-submicrometre MOS field-effect transistors (MOSFETs) and lateral double-diffused MOSFETs (LDMOSFETs). It is believed that the degradation is mainly due to the effects of the generated oxide-trapped charges and interface traps at the Si/SiO2 interface. In general, the large electric field is strongly localised in a well-defined region; therefore carrier injection and interface-trap creation are similarly concentrated. The strongly inharmonious characters of HC injection and resulting damage present a considerable challenge to both experimental and modelling efforts.The HC degradation behaviour of an n-channel LDMOS transistor is investigated under various stress conditions. By applying variable base charge pumping experiments, a consistent picture of the degradation mechanism can be depicted. HC-induced interface traps are generated in the channel region of the device, in the drift region below the thick field oxide and at the birds beak edge. The latter is shown to dominate the degradation of Idlin, which is the most critical parameter concerning HC lifetime in this specific device.

3D-Resurf: The integration of a p-channel LDMOS in a standard CMOS process

This paper presents an isolated high voltage (HV) p- channel lateral double diffused MOS (LDMOS) transistor integrated in a commercial 0.35mum CMOS process without any additional mask or implant steps and thus without increasing process complexity. It is shown that by the introduction of carefully controlled PWELL stripes in the drift region, an increase in breakdown voltages (VB) of LDMOS transistors from 10 to up to 25 V can be achieved. For the huge field of power management and automotive applications this approach of integration allows optimization for multiple voltage domains and guarantees high quality levels at an economical price level.

Universal PIN photodiodes in a 0.35μm BiCMOS mixed-signal ASIC technology

We present an improvement of monolithically integrated photodiodes in a p-type substrate of a commercial high-speed 0.35μm SiGe heterojunction bipolar transistor (HBT) BiCMOS technology. These photodetectors (PDs) combine low capacitance with high bandwidth and responsivity. Slight process modifications of the standard HBT process have been introduced in order to decrease leakage currents and enhance reach-through stability of the PDs. These modifications have been chosen carefully in order not to alter any other transistor parameters as shown in [1]. To enable low capacitances of the PDs very lightly p-doped epitaxially grown layers of different thicknesses over highly p-doped substrates have been investigated. The improvement becomes manifest, e.g. in a bandwidth of 557MHz and a responsivity of 0.19A/W of a finger photodiode at blue light and a reverse bias voltage of 4V in a 10μm cathode digit-spacing configuration. The capacitance of this finger photodiode is 150fF, overtopping the regular PIN photodiode published in [2] for the same light-sensitive area with a capacitance of 225fF. Results of detectors with interdigitated cathode distances of 5μm, 10μm, 15μm and 30μm are presented over the wide spectrum of technologically significant optical wavelengths from near-infrared to blue and ultraviolet. These detectors fulfil the requirements demanded by photodiode integrated circuits for universal backward compatible optical storage systems.