Timothy J. Koprowski

Advanced microprocessor test strategy and methodology

This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBMs high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached.

Testing the 400 MHz IBM generation-4 CMOS chip

This paper describes the design-for-test framework of the 400 MHz CMOS central processor (CP) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe the test sets required to test all portions of the design. This includes built-in self-test, array self-test, weighted random pattern generation, algorithmic pattern generation, and manual patterns. Tests are used to detect faults, static and dynamic, and to debug/diagnose chip failures characteristic to the function under test. The described tests ensure the highest reliability for the components within the system and the same test patterns can be applied from manufacturing all the way to the system level.

Testing the 500-MHz IBM S/390 microprocessor

The design-for-test framework of the 500-MHz CMOS central processor uses specific tests to ensure the highest reliability of components within a system. Some of the same test patterns are applied in chip manufacturing and system-level tests.

Weighted random test program generation for a per-pin tester

The authors present an overview of a comprehensive software system that serves as an automatic bridge between computer-aided-design- (CAD-) generated weighted random patterns (WRPs-) and a per-pin tester that incorporates dedicated hardware to support WRP testing. A test program generation system that integrates a level-sensitive-scan-design (LSSD-) based design system with a per-pin tester containing WRP hardware has been architected. This system generates complete test programs and permits the direct release of hundreds of ASIC (application-specific integrated circuit) devices into manufacturing. The benefits of low test data volume, improved test coverage, and finer diagnostic resolution provided by the WRP methodology are realized. The capture of delay defects is aided by the availability of several timing edges on a per-pin basis.<<ETX>>