Kunihiro Kasai

Mobility improvement for 45nm node by combination of optimized stress and channel orientation design

Performance improvement of CMOSFET by adopting <100>-channel direction with high tensile stress gate capping layer (GC liner-SiN) was demonstrated. For pMOSFET, higher hole mobility of <100>-channel and lesser short channel effect (SCE) results in 20% improvement of I/sub on/. In addition, this improvement was not sensitive to local uniaxial strain. For nMOSFET, similar to <110>-channel, 10% improvement of I/sub on/ is realized in <100>-channel with high tensile stress gate capping layer. Thus, this technology can improve the performance of nMOSFET and pMOSFET without introducing specific additional processes for nMOSFET and pMOSFET.

Low-resistivity poly-metal gate electrode durable for high-temperature processing

A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, A uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN/sub x/(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure was found to be thermally stable even after annealing at 800/spl deg/C. The sheet resistivity of the W(100 nm)/WN/sub x/(5 nm)/poly-Si(100 nm) structure is as low as 1.5 /spl Omega//spl par//spl square/ and independent of line-width from 0.52 /spl mu/m to 0.12 /spl mu/m. The sheet resistivity of this layer structure is 40% lower than that of the W(100 nm)/TiN(5 nm)/poly-Si structure. In addition, an equivalent circuit simulation showed that the measured contact resistivity of W and poly-Si in the W/WSiN/poly-Si system did not affect the gate RC delay time. Finally, a process integration of the poly-metal gate electrode is discussed. A SiN capped poly-metal structure was demonstrated.

W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs

In this paper, a new gate structure, W/WNx/poly-Si, was proposed as the breakthrough to combat the serious parasitic effect caused by RC delay of gate electrode in down-scaled CMOS devices. MOSFETs with the gate electrode structure were fabricated with a deep submicron CMOS process. As a result, 1.6/spl Omega//spl square/ gate sheet resistance without an increase in fine line gate was obtained. Moreover, it was demonstrated that the thin WNx layer formed by reactive sputtering can be an excellent barrier layer from the gate oxide integrity and W/poly-Si contact resistivity point of view.<<ETX>>

Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET

A guideline for n/sup /spl minus// fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, the greatest reduction in substrate current directly leads to the most reliable n/sup /spl minus// design for the FOLD structure. The current path modulation phenomenon due to the trapped charge at the n/sup /spl minus// extension region dominates the hot-carrier induced characteristics change for conventional lightly doped drain (LDD) structure with side-wall spacer. This phenomenon is minimized in the FOLD structure due to its higher controllability of the gate electrode than the LDD structure at the n/sup /spl minus// extension region. Furthermore, it was also confirmed that the 0.3 /spl mu/m optimized FOLD structure can achieve high circuit performance at 3.3 V operation, maintaining hot-carrier resistance. >

A high performance MOSFET design with highly controllable gate length and low RC delay multilevel interconnects technology for high speed logic devices

A high performance 0.3 /spl mu/m CMOS technology has been developed for high speed logic LSIs. A new gate formation technology achieved 0.3 /spl mu/m gate length MOSFETs by i-line based lithography and new ARC process. An optimized PLDD nMOSFET and buried channel pMOSFET achieved high current drivability without spoiling their reliability in 3.3 V operation. Moreover, ion implantation restricted only for channel/isolation region and SiOF low interlayer dielectric process reduced junction capacitance and wiring capacitance, respectively. Furthermore, CMP planarization process and selective CVD-W filling for contacts/vias achieved borderless design with the improvement of device density. The 0.3 /spl mu/m CMOS technology has performed 1.2 times improvement from conventional 0.35 /spl mu/m CMOS technology in a typical critical path of advanced MPUs.

Drain structure optimization for highly reliable deep submicron nMOSFETs with 3.3 V high performance operation

A guideline for optimization of the n/sup -/ fully gate overlapped structure (FOLD) has been established. Its reliability and performance were investigated in comparison with optimized LDD (lightly doped drain) structure (op.LDD). It is found that the superiority in reliability for the two structures is reversed below 3.5 V, and the optimized FOLD structure (op.FOLD) has higher reliability than the op.LDD structure. This is due to a discrepancy between peak electric field and current flow caused by high controllability of the gate electrode of the FOLD structure at the n/sup -/ extension region. The op.FOLD structure achieves high performance on the trend at 3.3 V, in spite of nonscaled gate oxide thickness (11 nm), which results from TDDB limitation for 3.3 V operation.<<ETX>>

High-performance 0.5 mu m CMOS technology for logic LSIs with embedded large capacity SRAMs

The optimum device design of 0.5 mu m CMOS for logic LSIs with embedded large-capacity SRAMs (static RAMs) with a 3.3 V supply voltage is proposed. In order to attain high performance with a 3.3 V supply, the p-MOSFET structure was designed and the gate oxide thickness and junction capacitance were optimized. A poly-Si load SRAM cell with a triple-well structure on p-substrate, WSi-polycide gate electrode, and triple-level metallization with W plug via holes were implemented. By careful design of each parameter and proper integration of the technologies, a high-performance 0.5 mu m CMOS with large-capacity cache memories was realized.<<ETX>>

A highly manufacturable high density embedded SRAM technology for 90 nm CMOS

A highly manufacturable high density embedded SRAM technology with a 0.8 /spl mu/m/sup 2/ cell for the 90 nm technology node has been developed. Based on a cell layout study by lithography simulation, both cell layout and key processes were carefully optimized and scaled down from those of 100 nm technology. The fabricated SRAM using 0.25 /spl mu/m well isolation and 0.1 /spl mu/m contacts showed good functionality down to VDD=0.6 V. An electrical fuse utilizing MOSFETs was also developed for redundancy to avoid Cu/low-k BEOL damage from laser blow.