Noriyuki Taoka

High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using

An ultrathin equivalent oxide thickness (EOT) HfO₂/Al₂O₃/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al₂O₃ layer between HfO₂ and Ge for suppressing HfO₂-GeO<i>x</i> intermixing, resulting in a low-interface-state-density (<i>D</i>_it) GeO<i>x</i>/Ge metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the <i>D</i>_it in 10¹¹ cm^-2·eV^-1 level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 cm²/V·s and peak electron mobilities of 754 and 689 cm²/V·s at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present HfO₂/Al₂O₃/GeO<i>x</i>/Ge gate stacks.

\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}

An electron cyclotron resonance (ECR) plasma postoxidation method has been employed for forming Al2O3/GeOx/Ge metal-oxide-semiconductor (MOS) structures. X-ray photoelectron spectroscopy and transmission electron microscope characterizations have revealed that a GeOx layer is formed beneath the Al2O3 capping layer by exposing the Al2O3/Ge structures to ECR oxygen plasma. The interface trap density (Dit) of Au/Al2O3/GeOx/Ge MOS capacitors is found to be significantly suppressed down to lower than 1011 cm−2 eV−1. Especially, a plasma postoxidation time of as short as 10 s is sufficient to reduce Dit with maintaining the equivalent oxide thickness (EOT). As a result, the minimum Dit values and EOT of 5×1010 cm−2 eV−1 and 1.67 nm, and 6×1010 cm−2 eV−1 and 1.83 nm have been realized for Al2O3/GeOx/Ge MOS structures with p- and n-type substrates, respectively.

Gate Stacks Fabricated by Plasma Postoxidation

An ultrathin equivalent oxide thickness (EOT) Al₂O₃/ GeO_x/Ge gate stack with a superior GeO_x/Ge metal-oxide-semiconductor (MOS) interface and p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) using this gate stack have been fabricated by a plasma post oxidation method. The properties of the GeO_x/ Ge MOS interfaces are systemically investigated, and it is revealed that there is a universal relationship between the interface state density (<i>D</i>_it) at the GeO<i>x</i>/Ge interface and the GeO_x interfacial layer thickness. Ge pMOSFETs on a (100) Ge substrate using the Al₂O₃/GeO_x/Ge gate stack have been demonstrated with an EOT down to 0.98 nm. It is found that the Ge pMOSFETs exhibit the peak hole mobility values of 515, 466, and 401 cm²/ V·s at an EOT of 1.18, 1.06, and 0.98 nm, respectively, which has much weaker EOT dependence than the trend of the hole mobility values reported so far, because of low <i>D</i>_it of the present gate stack in the ultrathin EOT region of ~1 nm.

Al2O3/GeOx/Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation

We have studied the impact of the Al2O3 inter-layer on interface properties of HfO2/InGaAs metal-oxide-semiconductor (MOS) interfaces. We have found that the insertion of the ultrathin Al2O3 inter-layer (2 cycle: 0.2 nm) can effectively improve the HfO2/InGaAs interface properties. The frequency dispersion and the stretch-out of C-V characteristics are improved, and the interface trap density (Dit) value is significantly decreased by the 2 cycle Al2O3 inter-layer. Finally, we have demonstrated the 1-nm-thick capacitance equivalent thickness in the HfO2/Al2O3/InGaAs MOS capacitors with good interface properties and low gate leakage of 2.4 × 10−2 A/cm2.

High-Mobility Ge pMOSFET With 1-nm EOT

We have demonstrated wide-range modulation of Schottky barrier height (SBH) of NiGe∕Ge(100) interfaces by using a valence mending adsorbate, sulfur, segregation during Ni germanidation. Implanted sulfur atoms, segregated during Ni germanidation, are expected to act as dangling bond terminator at the NiGe∕Ge interface. The experimental results show that the strong Fermi level pinning feature of NiGe∕Ge interfaces was alleviated, and SBH of NiGe∕n-Ge(100) gradually decreased from 0.61to0.15eV with an increase in the implanted sulfur dose. This method opens a way to realize Ge channel complementary metal-oxide-semiconductor field-effect transistors with metal source/drain.

\hbox{Al}_{2} \hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}

This paper demonstrates the successful fabrication of sub-100 nm Ge pMOSFETs with NiGe MSD and the high device performance, for the first time. It is also revealed that impurity profile engineering is still effective in controlling the electrical characteristics of short channel Ge MOSFET and that the concept of the universality for the inversion-layer mobility does hold even for Ge p-MOSFETs.

Gate Stack Fabricated by Plasma Post Oxidation

An ultrathin EOT Al<inf>2</inf>O<inf>3</inf>/GeO<inf>x</inf>/Ge gate stack with a superior GeO<inf>x</inf>/Ge MOS interface has been fabricated with a plasma post oxidation method. The properties of the ultra thin GeO<inf>x</inf>/Ge MOS interfaces are examined systemically, and it is revealed that there is a universal relationship between the D<inf>it</inf> at GeO<inf>x</inf>/Ge interface and the GeO<inf>x</inf> thickness, and a 0.5-nm-thick GeO<inf>x</inf> (0.35 nm EOT) is sufficient to suppress the D<inf>it</inf>. The Ge n- and p-MOSFETs using the Al<inf>2</inf>O<inf>3</inf>/GeO<inf>x</inf>/Ge gate stacks are fabricated on (100), (110) and (111) Ge. High mobility Ge n-MOSFETs with sub-nm EOT have been realized for the first time with record high mobilities of 937 and 691 cm²/Vs at EOT of 1.14 and 0.98 nm. It is found that the sufficient suppression of D<inf>it</inf> allows us to obtain high peak mobilities even in sub-nm EOT range, while further improvements in surface roughness and suppression of the density of remaining Coulomb scattering centers such as fixed charges and slow traps are still needed to further enhance the performances of Ge n- and p-MOSFETs.

1-nm-capacitance-equivalent-thickness HfO2/Al2O3/InGaAs metal-oxide-semiconductor structure with low interface trap density and low gate leakage current density

We have demonstrated sub-10-nm extremely thin body (ETB) InGaAs-on-insulator (InGaAs-OI) nMOSFETs on Si wafers with Al₂O₃ ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding process. We have fabricated the ETB InGaAs-OI nMOSFETs with channel thicknesses of 9 and 3.5 nm. The 9-nm-thick ETB InGaAs-OI n MOSFETs with a doping concentration (N_D) of 10¹⁹ cm^-3 exhibit a peak electron mobility of 912 cm²/V·s and a mobility enhancement factor of 1.7 times against the Si nMOSFET at a surface carrier density (N_s) of 3 ×10¹² cm^-2. In addition, it has been found that, owing to Al₂O₃ UTBOX layers, the double-gate operation improves the cutoff properties. As a result, the highest on-current to the lowest off-current (I_on/I_off) ratio of approximately 10⁷ has been obtained in the 3.5-nm-thick ETB InGaAs-OI nMOSFETs. These results indicate that the high-mobility III-V nMOSFETs can be realized even in sub-10-nm-thick channels.

Modulation of NiGe∕Ge Schottky barrier height by sulfur segregation during Ni germanidation

Abstract We review the technology of Ge1−xSnx-related group-IV semiconductor materials for developing Si-based nanoelectronics. Ge1−xSnx-related materials provide novel engineering of the crystal growth, strain structure, and energy band alignment for realising various applications not only in electronics, but also in optoelectronics. We introduce our recent achievements in the crystal growth of Ge1−xSnx-related material thin films and the studies of the electronic properties of thin films, metals/Ge1−xSnx, and insulators/Ge1−xSnx interfaces. We also review recent studies related to the crystal growth, energy band engineering, and device applications of Ge1−xSnx-related materials, as well as the reported performances of electronic devices using Ge1−xSnx related materials.

High Performance 60 nm Gate Length Germanium p-MOSFETs with Ni Germanide Metal Source/Drain

The impact of Si passivation (SP) on Ge metal-insulator-semiconductor interface properties and the inversion-layer mobility of Ge p-type metal-insulator-semiconductor field effect transistors (PMISFETs) were investigated by using the devices with different thicknesses of the SP layers. SP was effective in decreasing the total charged centers instead of the interface traps. As a result, the inversion-layer hole mobility of the Ge MISFET was significantly improved by introducing the SP layers of the appropriate thickness. This improvement is attributable to the reduction of the amount of the interface charges and the separation of the positions of mobile carriers and the interface charges by the SP layers.