SangHyeon Kim

1-nm-capacitance-equivalent-thickness HfO2/Al2O3/InGaAs metal-oxide-semiconductor structure with low interface trap density and low gate leakage current density

We have studied the impact of the Al2O3 inter-layer on interface properties of HfO2/InGaAs metal-oxide-semiconductor (MOS) interfaces. We have found that the insertion of the ultrathin Al2O3 inter-layer (2 cycle: 0.2 nm) can effectively improve the HfO2/InGaAs interface properties. The frequency dispersion and the stretch-out of C-V characteristics are improved, and the interface trap density (Dit) value is significantly decreased by the 2 cycle Al2O3 inter-layer. Finally, we have demonstrated the 1-nm-thick capacitance equivalent thickness in the HfO2/Al2O3/InGaAs MOS capacitors with good interface properties and low gate leakage of 2.4 × 10−2 A/cm2.

Sub-10-nm Extremely Thin Body InGaAs-on-Insulator MOSFETs on Si Wafers With Ultrathin

We have demonstrated sub-10-nm extremely thin body (ETB) InGaAs-on-insulator (InGaAs-OI) nMOSFETs on Si wafers with Al₂O₃ ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding process. We have fabricated the ETB InGaAs-OI nMOSFETs with channel thicknesses of 9 and 3.5 nm. The 9-nm-thick ETB InGaAs-OI n MOSFETs with a doping concentration (N_D) of 10¹⁹ cm^-3 exhibit a peak electron mobility of 912 cm²/V·s and a mobility enhancement factor of 1.7 times against the Si nMOSFET at a surface carrier density (N_s) of 3 ×10¹² cm^-2. In addition, it has been found that, owing to Al₂O₃ UTBOX layers, the double-gate operation improves the cutoff properties. As a result, the highest on-current to the lowest off-current (I_on/I_off) ratio of approximately 10⁷ has been obtained in the 3.5-nm-thick ETB InGaAs-OI nMOSFETs. These results indicate that the high-mobility III-V nMOSFETs can be realized even in sub-10-nm-thick channels.

\hbox{Al}_{2}\hbox{O}_{3}

We report that a Ni–InGaAs alloy can be used as a source/drain (S/D) metal for InGaAs metal–oxide–semiconductor field-effect transistors (MOSFETs), allowing us to employ the salicide-like self-align S/D formation. We also introduce Schottky barrier height (SBH) engineering process by increasing the indium content of InxGa1-xAs channels, which successfully reduces SBH down to zero. We propose a fabrication process for self-aligned metal S/D MOSFETs using Ni–InGaAs and demonstrate successful operation of the metal S/D InxGa1-xAs MOSFETs. The In0.7Ga0.3As MOSFETs exhibit an S/D resistance (RSD) that is 1/5 lower than that in P–N junction devices and a high peak mobility of 2000 cm2 V-1 s-1.

Buried Oxide Layers

We have demonstrated extremely-thin-body (ETB) (3.5 and 9 nm) InGaAs-on-insulator (InGaAs-OI) MOSFETs on Si substrates with Al<inf>2</inf>O<inf>3</inf> ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding (DWB). We have found that the ETB highly-doped InGaAs-OI n-channel MOSFETs without p-n junction can perform a normal MOSFET operation under front- and back-gate configuration and the double-gate operation can provide excellent on-current/off-current (I<inf>on</inf>/I<inf>off</inf>) properties of ∼10⁷ and the improved S factor even for InGaAs-OI MOSFETs with ND of 1×10¹⁹ cm⁻³.

Self-Aligned Metal Source/Drain InxGa1-xAs n-Metal–Oxide–Semiconductor Field-Effect Transistors Using Ni–InGaAs Alloy

We clarified that Fermi levels at InGaAs MOS interfaces are pinned inside conduction band (CB) and that this pinning severely degrades the effective mobility. Also, the energy position of the Fermi level pinning (FLP) is found to be tunable. It is experimentally shown that the increase in the difference between the FLP position and the CB minimum (CBM) leads to high mobility at high Ns region. Also, possible physical origin for this FLP is proposed.

Extremely-thin-body InGaAs-on-insulator MOSFETs on Si fabricated by direct wafer bonding

CMOS utilizing high-mobility III–V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III–V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III–V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III–V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III–V MOS device technologies, we mainly address the gate stack technology, III–V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III–V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III–V/Ge channels.

Impact of Fermi level pinning inside conduction band on electron mobility of In x Ga 1−x As MOSFETs and mobility enhancement by pinning modulation

We have studied the impact of atomic-layer-deposition (ALD) temperature on the HfO2/InGaAs metal-oxide-semiconductor (MOS) interface with a comparison to the Al2O3/InGaAs interface. It is found that the interface properties such as the C-V characteristics and the interface trap density (Dit) and the interface structure of HfO2/InGaAs have strong dependence on the ALD temperature, while the Al2O3/InGaAs interfaces hardly depend on it. As a result, we have achieved the HfO2/InGaAs interfaces with low Dit comparable to that in the Al2O3/InGaAs interface by lowering the ALD temperature down to 200 °C or less. Also, we have found that As2O3 and Ga2O3 formed at the interface during ALD increase with a decrease in the ALD temperature. Combined with the ALD temperature dependence of the electrical characteristics, the better C-V characteristics and the lower Dit obtained at the lower ALD temperature can be explained by the As2O3 and Ga2O3 passivation of the HfO2/InGaAs interfaces, which is consistent with a repor...

III–V/Ge channel MOS device technologies in nano CMOS era

In this paper, we have investigated the electron transport properties under two types of mobility enhancement engineering, which are channel strain and MOS interface buffer engineering. We have demonstrated epitaxial-based biaxially strained In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs. Tensile strained In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs shows high peak mobility of 2150 cm²/Vs. Furthermore, we have demonstrated high performance InAs-OI(-on insulator) MOSFETs on Si substrate with MOS interface buffer layer by direct wafer bonding, showing high peak mobility of 3180 cm²/Vs. The scattering mechanisms for the electron mobility in thin body In<inf>x</inf>Ga<inf>1−x</inf>As(InAs)-OI MOSFETs have been systematically analyzed and identified, for the first time.

Impact of atomic layer deposition temperature on HfO2/InGaAs metal-oxide-semiconductor interface properties

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for improving the channel mobility and the MOS interface properties with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeOx/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low Dit and high mobility. HfO2/Al2O3/GeOx/Ge gate stacks exhibit record high electron and hole mobility under EOT of 0.76 nm. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm. The results of low Dit HfO2/Al2O3/InGaAs stacks with CET of 1.08 nm are also presented. A strategy to enhance electron mobility in InGaAs MOSFETs on a basis of physical understanding of the MOS interface properties including high Dit inside the conduction band is also addressed.

Enhancement technologies and physical understanding of electron mobility in III–V n-MOSFETs with strain and MOS interface buffer engineering

The extremely thin body (ETB) InGaAs-on-insulator (-OI) metal–oxide–semiconductor field-effect transistors (MOSFETs) on Si substrates were demonstrated by using Ni–InGaAs alloy metal source/drain (S/D). It has been found that a light doping concentration of ~1016 cm-3 and indium-rich InGaAs channels (In0.7Ga0.3As) provide a high mobility of 1700 cm2 V-1 s-1 even in the channel thickness of 10 nm. This is the first demonstration of ETB III–V-OI MOSFETs combined with the metal S/D technology. We have also achieved excellent ID–VG characteristics with an Ion/Ioff ratio of over 105 and low SS of 120 mV/dec in 5-nm-thick In0.7Ga0.3As-OI MOSFETs.