Toshifumi Kobayashi

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure

A 288-kb (8 K words*36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder is described. The stacked-capacitor structure results in a very compact dynamic CAM cell (66 mu m/sup 2/) which is operationally stable. The novel hierarchical priority encoder reduces the circuit area and power dissipation. In addition, a new priority decision circuit is introduced. The chip size is 10.3 mm*12.0 mm using a 0.8- mu m CMOS process technology. A typical search cycle time of 150 ns and a maximum power dissipation of 1.1 W have been obtained using circuit simulation. In fabricated CAM chips, the authors have verified the performance of a search operation at a 170-ns cycle and have achieved a typical read/write cycle time of 120 ns. >

A built-in Hamming code ECC circuit for DRAMs

An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique. >

A 288-kbit fully parallel content addressable memory using stacked capacitor cell structure

The authors describe a 288-kb (8 K words*36-b) fully parallel CAM (content addressable memory) LSI using a compact dynamic CAM cell (66 mu m/sup 2/) with stacked capacitor structure and a novel hierarchical priority encoder. The chip size is 10.3*12.0 mm/sup 2/, and the typical cycle time is 150 ns using circuit simulation. This CAM LSI performs large-scale search operations very efficiently, and therefore has the possibility of broad applications to high-performance artificial-intelligence machines and relational database systems.<<ETX>>

A fast 256/spl times/4 CMOS DRAM with a distributed sense and unique restore circuit

A 256 K/spl times/4 CMOS dynamic RAM has been fabricated using a double-poly single-metal n-well CMOS technology with a distributed sense and unique restore (DSR) circuit. The bit line is divided into two segment bit lines, and both n-channel and p-channel latches are connected to each segment bit line in the DSR structure, which provides an improved signal-to-noise ratio and saves the silicon area for decoders and an extra metal layer. The sensing scheme of the distributed sense and unique restore circuit is discussed. The novel bit-line precharge voltage (VPR) generator, which actually holds the VPR at V/SUB cc//2, is described.

A 70ns 256K DRAM with bitline shielding structure

THE DESIGN of DRAMS with the smallest die, the fastest access time and the widest operating margin, has been receiving major attention. This paper will report on the development of a 70ns 256K x l b DRAM, using bitline shielding. The chip, whose die area is 3.6 x 8.4mm2 ( = 30.2mm2), is enclosed in a plastic 16-pin, 300mil dual-in-line package. The open-bitline architecture of the array (Figure 1 ) was chosen to provide improved speed, smaller area and better signal level’. However, non-common mode noise occurs from the coupling of column address lines into the bitlines during the sensing period which accounts for 23% of the chip access time. Figure 2 shows the bitline shielding technique applied to the memory. A third-level polysilicon layer, which is connected to the ground, acts as a shielding plate between the diffused bitlines and aluminum column address lines. This shielding plate absorbs non-common mode noises. The polysilicon is also used as bitline material’ ; Figure 3. The time constant of the bitline is one half that of the diffused equivalent. The third level bitlines and the boosted wordlines serve to transfer the signals from the memory cells to the sense nodes rapidly. Moreover, the Vcc cell plate allows effective use of the small memory cell area (63.5pm) and leads to a storage capacitance 9% larger than a grounded cell plate. Thus, it is possible to transfer the memory cell data faster and more efficiently to the sense node, in spite of the smaller cell and die area. Sensing period of the output preamplifiers has also been improved. As shown in Figure 4, only one set of I /O lines is connected selectively to the preamplifier nodes at a time.

A 47ns 64KW &#215; 4b CMOS DRAM with relaxed timing requirements

A 256Kb DRAM which eliminates the positive-going RAS signal edge from the internal timing by a time-out function, will be reported. The access time is 47ns with predecoding, and power dissipation is 115mW at 200ns cycle time.