Hirokazu Miyoshi

Novel electron injection method using band-to-band tunneling induced hot electrons (BBHE) for flash memory with a P-channel cell

A novel electron injection scheme for flash memory is proposed, where band-to-band tunneling induced hot electrons (BBHE) are employed in a P-channel cell. This proposed method ensures the realization of high program efficiency, high scalability and hot-hole-injection-free operation. We also demonstrate an application of the method to DINOR (DIvided bit-line NOR) program operation. An ultra-high-speed programming of 60 nsec/Byte can be achieved with a leakage current less than 1 mA by utilizing 512 Byte parallel programming. This new DINOR flash memory is shown to be the most promising for the realization of a low-voltage, high-performance and high-reliability flash memory of 64 Mbits and beyond.

A quantitative analysis of time-decay reproducible stress-induced leakage current in SiO/sub 2/ films

In the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress, three reproducible stress-induced leakage current (SILC) components have been found for the repeated unipolar gate-voltage scans in 9.2 nm wet oxides. To clarify the mechanisms of these current components, a quantitative analysis has been developed. By precisely modeling the phonon assisted tunneling process, it has been shown that the E-J and t-J characteristics of the reproducible current components can be completely simulated as electron tunneling processes into the neutral traps, each with a single trap level. From this analysis, the physical parameters of the traps have been estimated with a reasonable degree of accuracy. Furthermore, the increase in distribution of the neutral trap density toward both the SiO/sub 2/ interfaces has also been estimated.

A quantitative analysis of stress induced excess current (SIEC) in SiO/sub 2/ films

The low-level stress induced excess current (SIEC) characteristics of 92 /spl Aring/ wet oxide are investigated in detail. As a result of the systematic investigations of the low-level E-J characteristics and the corresponding changes of net oxide charge, we have found that SIEC can be interpreted as electron tunneling processes into five kinds of different traps. As for the reproducible SIEC components, a quantitative analysis has been developed. By precisely modeling the trap assisted tunneling process, it has been shown that the E-J and t-J characteristics of the pretunneling region can be completely simulated as an electron tunneling process into the neutral trap. Using this analysis, it has been found that the local neutral trap density in bulk SiO/sub 2/ remains constant under the same hole fluence Qhole, regardless of the electric field strength during V/sub g/>0 FN stresses. In consequence, it has been concluded that the neutral trap has been created by holes injected into the oxide during the stresses.

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V/sub cc/ and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 /spl mu/m, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8/spl times/1.6 /spl mu/m/sup 2/ and the chip measures 5.8/spl times/5.0 mm/sup 2/. The divided bit line structure realizes a small NOR type memory cell. >

Identification of stress-induced leakage current components and the corresponding trap models in SiO/sub 2/ films

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the-current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components.

A C-switch cell for low-voltage and high-density SRAMs

We propose a novel static random access memory (SRAM) cell named complementary-switch (C-switch) cell. The proposed SRAM cell features: (1) C-switch in which an n-channel bulk transistor and a p-channel TFT are combined in parallel; (2) single-bit-line architecture; (3) gate-all-around TFT (GAT) with large ON-current of /spl mu/A order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-switch cell is built with only a triple poly-Si and one metal process using 0.3 /spl mu/m design rules.

Origin of positive charge generated in thin SiO/sub 2/ films during high-field electrical stress

The characteristics of electron capture in a 131-/spl Aring/ silicon dioxide after hot-hole injection have been studied, which have been compared with those after high-field Fowler-Nordheim (FN) electron injection. After hole injection from the silicon substrate into the oxide, positive charges accumulated in the oxide and electrons could be captured even at low oxide fields only under the positive gate polarity. The charge centroid of the captured electrons was near the substrate-SiO/sub 2/ interface. The low-field electron capture can be explained based on the electron tunneling from the substrate into the positive charge and neutral trap centers created near the substrate-SiO/sub 2/ interface. In order to investigate the initial stage of the oxide degradation due to high-field FN stress, electrons were injected from the gate and the charge fluence was selected to be -1.0 C/cm/sup 2/. After the high-field stress, positive charges appeared in the oxide and electrons were captured only under the positive gate polarity by the positive charge and neutral trap centers, which were distributed near the interface. These facts are explained on the basis of the model describing that hole injection and trapping are the dominant causes for the generation of the positive charge centers during high-field FN stress.

Influence of holes on neutral trap generation

Using a newly proposed method for estimating the neutral trap density, generation characteristics of the neutral trap during various stress types have been investigated. From the analysis of the trap-generation kinetics, two types of trap generation closely related to holes have been identified. At the first stage of stress application, holes interact with the pre-existing structural origins of the neutral traps, then the neutral traps are generated. Influence of hole energy on this type of trap generation is also identified. After that, as holes pass, they also create the structural origins of the traps. The holes interact with these structural origins and the neutral traps are generated as a secondary effect. Thus, the increase in the neutral trap density shows up clearly with increase in the hole fluence. The stress-strength dependence of the increase in the neutral trap density can also be interpreted in terms of the influence of hole energy on the trap generation.

ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed.<<ETX>>

Suppression of delay time instability on frequency using field shield isolation technology for deep sub-micron SOI circuits

It was demonstrated that Field Shield (FS) isolation technology can suppress the delay time instability depending on operating frequency. FS isolation technology has been proposed to tie the body potential without any area penalties in gate array. Moreover, the effect of body resistance on the instability was also investigated using device simulation.