Tomotoshi Sato

Mechanical effects of copper through-vias in a 3D die-stacked module

Mechanical effects of copper through-vias formed in silicon dies in a three dimensional module, in which four bare-dies with copper through-vias are vertically stacked and electrically connected through the copper-vias and metal bumps, were numerically and experimentally studied. To examine the mechanical effects caused by the existence of the copper through-vias in a rigid silicon-chip, a series of stress analyses, related simple mechanical tests, and reliability tests were carried out. All these results show that the copper through-via has unique effects on the stress distribution caused by thermal mismatch and on the interconnection reliability in the 3D die-stacked module. In particular, it was found that the developed micro copper through-via is reliable because the stress distribution due to thermal load is close to the hydrostatic pressure condition, and enhances chip-to-chip interconnection reliability because the copper-via restrains the plastic deformation of a gold bump during temperature cycling.

Thermal characterization of bare-die stacked modules with Cu through-vias

This paper describes the thermal characteristics of three dimensional (3-D) modules where four bare-dies with Cu through-vias are vertically stacked and electrically connected through the Cu-vias and the metal bumps. To realize more accurate thermal analysis for the 3D-modules in the earlier stage of the process development, a series of simple thermal resistance measurements by laser-flash method and parametric numerical analyses have been carried out. First, the thermal effects of the interface between two layers were quantified on the basis of the results of the laser-flash method. Second, using experimental interfacial thermal resistance, the thermal conduction analyses for 3D-modules were carried out. The key parameters governing the thermal performance of bare-die stacked modules and the design guideline of the thermal bumps are presented.

Superfine flip-chip interconnection in 20/spl mu/m-pitch utilizing reliable microthin underfill technology for 3D stacked LSI

The superfine flip-chip interconnection was evaluated on the chip on chip (COC) structure with the daisy chain patterns. The electroplated Au bumps allocated on the periphery of the Si chip in 20/spl mu/m-pitch were applied to the experiments. The underfill resin incorporated with the hyperfine filler particles achieved the acceptable reliability in the temperature cycling test (TCT) of the micro joints. The results showed no failure over 1,000 cycles with the optimized underfill resin. The finite element method (FEM) analysis found that the hyperfine filler particles in the underfill resin could reduce the equivalent plastic strain of micro-Au-bumps less than 1.0%, especially concentrated around the center of the interconnection at the bonding interface during TCT. In addition, the results in TCT with the optimized underfill resin were superior to the results with no underfill resin even as the results on COC structure. In case of the result with no underfill, it was found that the breakage occurred in the different mode as the results with the underfill resin, which was supposed from the dissimilar distribution of the strain due to the difference of the coefficient of thermal expansion (CTE) between the Au bumps and the Si devices.