Takashi Tokairin

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of , where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of at a 1-MHz offset frequency. The chip core occupies 0.37 and the measured power consumption is 8.1 mA from a 1.2-V power supply.

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

A low-power dual-band triple-mode WLAN CMOS transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively

A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC

All-digital phase-locked loops (ADPLLs) offer the advantages of eliminating the large on-chip passive filter and not suffering from poor low-supply-voltage operation with process scaling [1,2]. However, there is a challenge in achieving low power consumption at the same time as providing the low phase noise required in modern wireless systems like WiFi and WiMAX that have higher-order modulations. Recently, efforts improve phase noise have been accomplished by increasing the time resolution of the time-to-digital converter (TDC) using a gated ring-oscillator structure by using a multipath ring oscillator [3], 2-step structures based on a vernier delay line [4] or a time-amplifier [5,6]. However, these structures require large power consumption because they require many continuously operating high-speed delay-stages.

Analytical Expression of Quantization Noise in Time-to-Digital Converter Based on the Fourier Series Analysis

This paper describes a simple, analytical expression for quantization noise in a time-to-digital converter (TDC) based on Fourier-series analysis. We analyzed inverter propagation-delay variations due to fluctuations in the threshold voltage, and here we also discuss phase noise in an all-digital phase locked loop (ADPLL). The large standard deviation in the threshold voltage degrades phase noise even under short inverter-delay conditions. Increasing the gate area of transistors led to low phase noise due to threshold variations, but greatly increased power consumption. The paper also discusses TDC power reduction method without degrading quantization noise. Our analytically predicted results agreed well with the data obtained from a Spectre-RF simulator.

A 0.18-/spl mu/m CMOS Low-spurious Local Signal Generator for MB-OFDM UWB Radio

This paper presents a new single PLL and single SSB-mixer architecture for a local signal generator of the Mode-1 MB-OFDM UWB systems. Using a VCO running at 8976 MHz and a divide-by-2 circuit, it can provide a 4488-MHz carrier signal with low-spurious levels, which is required to meet the spectrum mask requirements being considered in Japan and Europe. A divide-by-8.5/17 circuit using double-edge triggered operation is introduced to obtain 3432-and 3960-MHz carriers from the same VCO in order to save die area. This circuit generates 1056-and 528-MHz signals, and the required signals can be obtained by mixing these with 4488 MHz signal. The core area of the local signal generator fabricated in a 0.18-mum CMOS technology is 0.67 mm2. The spurious levels for the 4488-MHz carrier are below -41 dBc.