Masanori Izumikawa

A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-/spl mu/m CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs.

A 0.9 V 100 MHz 4 mW 2 mm/sup 2/ 16 b DSP core

A 0.25 /spl mu/m CMOS 0.9 V 100 MHz 4 mW 2 mm/sup 2/ DSP core is composed of a 16 b multiplier, a 32 b adder, an 8 kb SRAM, and a PLL. Voltage-scalable circuits capable of operating at 0.5 V to 2.5 V and level-converting interface circuits applied to the DSP make it suitable for multiple-supply-voltage portable systems.

100 MHz, 0.55 mm/sup 2/, 2 mW, 16-b stacked-CMOS multiplier-accumulator

A 16-b multiplier-accumulator with stacked CMOS has been developed. It can be used for the digital signal processors which, as main parts of multimedia portable terminals, are required to have low power consumption and high processing speed. The stacked-CMOS logic circuit, which has high-speed and low-power characteristics, and optimization techniques are employed to attain a low power dissipation value of 2 mW at 100 MHz operation. Its area is 0.55 mm/sup 2/, and the transistor density is two times that of conventional multiplier-accumulators. The fabrication technology is a 0.25-/spl mu/m CMOS double layer Al process.