Masaru Haraguchi
Renesas Electronics
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Publication
Featured researches published by Masaru Haraguchi.
international solid-state circuits conference | 2007
Masaru Haraguchi; Tokuya Osawa; Akira Yamazaki; Chikayoshi Morishima; Toshinori Morihara; Yoshikazu Morooka; Yoshihiro Okuno; Kazutami Arimoto
An experimental chip for a 32b wide DDR2 SDRAM interface for SoC is fabricated in a 90nm CMOS process and achieves 960Mb/s/pin operation. Impedance-calibration circuits and flexible round-trip circuits in a continuous-adaptive DDR2 interface are used to suppress skew and allow a longer round-trip time.
IEICE Transactions on Electronics | 2005
Akira Yamazaki; Fukashi Morishita; Naoya Watanabe; Teruhiko Amano; Masaru Haraguchi; Hideyuki Noda; Atsushi Hachisuka; Katsumi Dosaka; Kazutami Arimoto; Setsuos Wake; Hideyuki Ozaki; Tsutomu Yoshihara
The voltage margin of an embedded DRAMs sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.
Archive | 2012
Kan Murata; Hideyuki Noda; Masaru Haraguchi
Archive | 2002
Mitsuya Kinoshita; Tetsushi Tanizaki; Masaru Haraguchi; Katsumi Dosaka
Archive | 2007
Masaru Haraguchi; Takeshi Fujino
Archive | 2003
Takayuki Gyohten; Masaru Haraguchi; Fukashi Morishita
Archive | 2007
Chikayoshi Morishima; Tokuya Osawa; Masaru Haraguchi; Yoshihiro Yamashita
Archive | 2004
Masaru Haraguchi
Archive | 2002
Masaru Haraguchi; Tetsushi Tanizaki
Archive | 2004
Atsuo Mangyo; Masaru Haraguchi; Akira Yamazaki
