Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Tetsushi Tanizaki is active.

Publication


Featured researches published by Tetsushi Tanizaki.


international solid-state circuits conference | 2003

A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write

Y. Taito; Tetsushi Tanizaki; Mitsuya Kinoshita; F. Igaue; Takeshi Fujino; Kazutami Arimoto

A high density memory (HDRAM) for SoC with SRAM interface is described. This macro achieves no-wait fast random-cycle operation owing to a sense-synchronized read/write scheme. A 4Mb test device is fabricated in a 0.15/spl mu/m process and achieves 143MHz operation. Its size and standby power are 4.59mm/sup 2/ and 92mW, which are 30% and 4.8%, respectively, of an embedded SRAM macro fabricated identically.


Archive | 1998

Semiconductor memory device capable of increasing chip yields while maintaining rapid operation

Mako Kobayashi; Tetsushi Tanizaki; Kazutami Arimoto; Teruhiko Amano; Takeshi Fujino; Takahiro Tsuruda; Fukashi Morishita; Mitsuya Kinoshita


Archive | 1998

Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement

Tetsushi Tanizaki; Mitsuya Kinoshita; Takeshi Fujino; Takahiro Tsuruda; Fukashi Morishita; Teruhiko Amano; Kazutami Arimoto; Mako Kobayashi


Archive | 2000

High speed operable semiconductor memory device with memory blocks arranged about the center

Teruhiko Amano; Takahiro Tsuruda; Kazutami Arimoto; Tetsushi Tanizaki; Takeshi Fujino; Mitsuya Kinoshita; Fukashi Morishita; Mako Kobayashi


Archive | 2003

Semiconductor memory device having a circuit for fast operation

Tetsushi Tanizaki; Katsumi Dosaka; Mikio Asakura


Archive | 1993

Dynamic random access memory device suitable for shortening time required for testing self-refresh function

Tetsushi Tanizaki


Archive | 2000

Semiconductor memory device that can have power consumption reduced during self refresh mode

Tetsushi Tanizaki


Archive | 1993

Semiconductor memory device including additional memory cell block having irregular memory cell arrangement

Tetsushi Tanizaki


Archive | 1998

Semiconductor memory device allowing writing of desired data to a storage node of a defective memory cell

Tetsushi Tanizaki; Masaki Tsukude


Archive | 2000

Semiconductor memory device having a test mode setting circuit

Tetsuo Kato; Takayuki Miyamoto; Tetsushi Tanizaki; Mikio Asakura

Collaboration


Dive into the Tetsushi Tanizaki's collaboration.

Researchain Logo
Decentralizing Knowledge