Mauro Dell'Orso

VLSI structures for track finding

Abstract We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This “machine” is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of “patterns”. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out.

The CDF Central and Endwall Hadron Calorimeter

Abstract The CDF central and endwall hadron calorimeter covers the polar region between 30° and 150° and a full 2π in azimuth. It consists of 48 steel-scintillator central modules with 2.5 cm sampling and 48 steel-scintillator endwall modules with 5.0 cm sampling. A general description of the detector is given. Calibration techniques and performance are discussed. Some results of the test beam studies are shown.

A VLSI processor for fast track finding based on content addressable memories

We describe a VLSI processor for pattern recognition based on content addressable memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among 2/sup 96/ possible combinations, in just a few 40 MHz clock cycles. We have developed this device (called the AMchip03 processor) for the silicon vertex trigger (SVT) upgrade at CDF using a standard-cell VLSI design methodology. This approach provides excellent pattern density, while sparing many of the complexities and risks associated to a full-custom design. On the other hand, the cost performance ratio is well more than one order of magnitude better than an FPGA-based design. This processor has a flexible and easily configurable structure that makes it suitable for applications in other experimental environments. We look forward to share this technology.

A Two Level Fastbus Based Trigger System for CDF

Abstract We describe a two level FASTBUS based trigger processor designed and built for the CDF detector at the Fermilab p p collider. The Level 1 decision is based on the global energy deposition in the calorimeters as well as on the presence of muon candidates and stiff tracks in the central drift chamber. The Level 1 decision is made in the 3.5 μs between beam crossings, incurring no deadtime while reducing a raw event rate of 50–75 kHz to a few kHz. The remaining events are passed on to Level 2. The Level 2 decision is driven by the topology of the event, operating on calorimeter clusters, central stiff tracks and muon candidates. Level 2 is designed to reduce the rate to 1–100 Hz, incurring less than 10% deadtime, before initiating readout of all the detector elements. A large fraction of the trigger hardware is used for both the Level 1 and Level 2 decisions.

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

Proposal of a data sparsification unit for a mixed-mode MAPS detector

The Italian silicon-detectors-with-low-interaction-with material collaboration (SLIM5) has designed, fabricated and tested several prototypes of CMOS monolithic active pixel sensors (MAPS). This paper shows the design of a new mixed-mode chip prototype composed of a bidimensional matrix of pixels, and of an off-pixel digital readout sparsification circuit. The readout logic is based on commercial standard cells and implements an optimized non token readout technique. Also, a MAPS emulator software toool is presented. The project is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future high-energy physics experiments. The readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors.

The CDF trigger silicon vertex tracker (SVT)

The design is presented for a device presently being built to perform on line track finding and reconstruction for the CDF (Collider Detector at Fermilab) Silicon Vertex Detector (120 k channels). This device will provide track impact parameter information for the CDF Level 2 trigger decision, thus allowing CDF to trigger on events containing a long lived particle, in particular a b-quark. It will be the first device with such a capability installed at a proton-antiproton collider. The capability to separate b decays early in the trigger process is vital to the CDF program to collect a high statistic b sample to attack the study of CP violation in the b sector. Moreover SVT will open access to non-leptonic b decays like B/spl rarr//spl pi//spl pi/. >

The fast tracker processor for hadronic collider triggers

Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above few GeV and search secondary vertexes within typical level-2 times.

Associative memory design for the fast track processor (FTK) at ATLAS

We propose a new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new associative memory project: it maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.

The SVT Hit Buffer

The Hit Buffer is part of the Silicon Vertex Tracker [1], a trigger processor dedicated to the reconstruction of particle trajectories in the Silicon Vertex Detector [2] and the Central Tracking Chamber of the Collider Detector at Fermilab. The Hit Buffer is a high speed data-traffic node, where thousands of words are received in arbitrary order and simultaneously organised in an internal structured data base, to be later promptly retrieved and delivered in response to specific requests. The Hit Buffer is capable to process data at a rate of 25 MHz, thanks to the use of special fast devices like Cache-Tag RAMs and high performance Erasable Programmable Logic Devices from the XILINX XC7300 family.