Michał Grobelny

Hardware Behavioural Modelling, Verification and Synthesis with UML 2.x Activity Diagrams

Modelling of hardware behavior is the fundamental process of hardware design project. Possible specification techniques, like UML 2.x Activity Diagrams or Control Interpreted Petri Nets, all have its advantages and disadvantages. Combing the accessibility of UML and full support for formal verification of Petri nets may significantly improve design quality. The article propose a system supporting logic controllers development, starting from a specification, going through formal verification (including model checking), and ending with synthesis.

Decomposition, validation and documentation of control process specification in form of a Petri net

The article focuses on some aspects regarding logic controller design. Control process is formally specified using interpreted Petri nets. It is then formally verified against behavioral properties using model checking technique and temporal logic. Formal specification can also be documented as UML activity diagram. One can then benefit from advantages of both specification techniques - Petri nets with a wide range of mathematical support and user-friendly UML activity diagrams. An interpreted Petri net can also be decomposed into state machine components (SMCs), each of them to be implemented in a separate module of FPGA device.

Model Checking of UML Activity Diagrams in Logic Controllers Design

The article presents a novel approach to model checking of UML activity diagrams (in version 2.x) for logic controller specification. A novel idea to design embedded systems by means of activity diagrams is introduced, using the previously proposed rule-based logical model suitable both for formal verification and logic synthesis. As the result implemented solution is consistent with the verified specification delivered in form of an user-friendly UML activity diagram. The idea is presented on a simple control process of two vehicles movement. Model checking technique is used to verify system model against behavioral properties expressed in temporal logic. In case of detected errors appropriate counterexamples are generated.

Design and Verification of Real-Life Processes With Application of Petri Nets

This paper focuses on the design and verification methods of distributed logic controllers supervising real-life processes. Such systems have to be designed very carefully and precisely in order to operate flawlessly and to meet user needs. We propose to use interpreted Petri nets as modeling formalism. A new design flow of distributed logic controllers is introduced. The methodology covers the development process from the specification stage to the final implementation of the controller in the distributed devices. In the proposed solution, the system is decomposed into separate modules that form a distributed system. Furthermore, the specification (before and after the decomposition process) is formally verified with the application of the model checking technique against predefined behavioral requirements. Finally, the system is implemented in real devices. The usage of formal methods and double model checking ensure the correct functionality of the designed distributed logic controller. The theoretical approach is supplemented by the practical experiments. Furthermore, the proposed idea is illustrated by an example of a smart home system.

Logic controller design system supporting UML activity diagrams

The paper introduces a logic controller design system, called PNAD, supporting UML activity diagrams in version 2.x as a semi-formal specification technique. The system enables transformation of activity diagrams into control Petri nets, their formal verification using model checking technique and the nuXmv tool, generation of synthesizable code in hardware description language VHDL and generation of C code for microcontrollers. The benefits include the support for discrete event system development since the specification till prototype implementation. Additionally, reverse transformation from control Petri nets into UML activity diagrams is also possible. The internal representation of diagrams is based on XML files. The usage of proposed system is illustrated on an example of concrete production process.

UML activity diagram swimlanes in logic controller design

Logic controller behavior can be specified using various techniques, including UML activity diagrams and control Petri nets. Each technique has its advantages and disadvantages. Application of both specification types in one project allows to take benefits from both of them. Additional elements of UML models make it possible to divide a specification into some parts, considered from other point of view (logic controller, user or system). The paper introduces an idea to use UML activity diagrams with swimlanes to increase the understandability of design models.

Design and verification of distributed logic controllers with application of Petri nets

The paper deals with the designing and verification of distributed logic controllers. The control system is initially modelled with Petri nets and formally verified against structural and behavioral properties with the application of the temporal logic and model checking technique. After that it is decomposed into separate sequential automata that are working concurrently. Each of them is re-verified and if the validation is successful, the system can be finally implemented.

UML activity diagrams in requirements specification of logic controllers

Logic controller specification can be prepared using various techniques. One of them is the wide understandable and user-friendly UML language and its activity diagrams. Using formal methods during the design phase increases the assurance that implemented system meets the project requirements. In the approach we use the model checking technique to formally verify a specification against user-defined behavioral requirements. The properties are usually defined as temporal logic formulas. In the paper we propose to use UML activity diagrams in requirements definition and then to formalize them as temporal logic formulas. As a result, UML activity diagrams can be used both for logic controller specification and for requirements definition, what simplifies the specification and verification process.

Implementation of www server in SoPC

In this paper implementation of WWW server in SoPC (System-on-Programmable-Chip) is described. Reasons for implementing a WWW server in SoPC are explained. Moreover, the basis architecture of SoPC will be mentioned. The proposed system is divided into two parts. First part is software implemented for microprocessor, which consists of operating system, web server and additional functionalities. Second part is a control process that is implemented in FPGA structure. The software solution is based on the Nut/OS operating system and web server implemented in it. The dynamic reconfiguration is also discussed.

C code generation from Petri-net-based logic controller specification

The article focuses on programming of logic controllers. It is important that a programming code of a logic controller is executed flawlessly according to the primary specification. In the presented approach we generate C code for an AVR microcontroller from a rule-based logical model of a control process derived from a control interpreted Petri net. The same logical model is also used for formal verification of the specification by means of the model checking technique. The proposed rule-based logical model and formal rules of transformation ensure that the obtained implementation is consistent with the already verified specification. The approach is validated by practical experiments.