Remigiusz Wisniewski

Decomposition, validation and documentation of control process specification in form of a Petri net

The article focuses on some aspects regarding logic controller design. Control process is formally specified using interpreted Petri nets. It is then formally verified against behavioral properties using model checking technique and temporal logic. Formal specification can also be documented as UML activity diagram. One can then benefit from advantages of both specification techniques - Petri nets with a wide range of mathematical support and user-friendly UML activity diagrams. An interpreted Petri net can also be decomposed into state machine components (SMCs), each of them to be implemented in a separate module of FPGA device.

Application of comparability graphs in decomposition of Petri nets

In the article we present a new algorithm of Petri net decomposition into State Machine Components (SMCs). The idea bases on the application of the comparability graph theory. The comparability graphs are classified as a subclass of the perfect graphs and have unique properties. If a graph belongs to the comparability class, many problems (like graph coloring, maximal clique problem) can be solved in polynomial time. Therefore, if the sequentiality graph of a Petri net belongs to comparability class, the whole decomposition process turns to be polynomial. The preliminary experiments have demonstrated the effectiveness of the proposed idea. Over 90% of concurrency and sequentiality graphs of tested benchmarks belong to the comparability class. The efficiency is even higher if the Petri net class is reduced to the EFC (Extended Free-Choice).

Application of an Exact Transversal Hypergraph in Selection of SM-Components

The paper deals with the application of the hypergraph theory in selection of State Machine Components (SM-Components) of Petri nets [1,2].As it is known, Petri nets are widely used for modeling of concurrency processes. However, in order to implement the concurrent automaton, an initial Petri net ought to be decomposed into sequential automata (SM-Components), which can be easily designed as an Finite-State-Machine (FSM) or Microprogrammed Controller [3]. The last step of the decomposition process of the Petri nets is selection of SM-Components. This stage is especially important because it determines the final number of sequential automata. In the article we propose a new idea of SM-Components selection. The aim of the method is reduction of the computational complexity from exponential to polynomial. Such a reduction can be done if the selection hypergraph belongs to the exact transversal hypergraphs (xt-hypergraphs) class. Since the recognition and generation of the first transversal in the xt-hypergraphs are both polynomial, the complete selection process can be performed in polynomial time. The proposed ideas are an extension of the concept presented in [1].The proposed method has been verified experimentally. The conducted investigations have shown that for more than 85% of examined Petri nets the selection process can be done via xt-hypergraphs.

Design and Verification of Real-Life Processes With Application of Petri Nets

This paper focuses on the design and verification methods of distributed logic controllers supervising real-life processes. Such systems have to be designed very carefully and precisely in order to operate flawlessly and to meet user needs. We propose to use interpreted Petri nets as modeling formalism. A new design flow of distributed logic controllers is introduced. The methodology covers the development process from the specification stage to the final implementation of the controller in the distributed devices. In the proposed solution, the system is decomposed into separate modules that form a distributed system. Furthermore, the specification (before and after the decomposition process) is formally verified with the application of the model checking technique against predefined behavioral requirements. Finally, the system is implemented in real devices. The usage of formal methods and double model checking ensure the correct functionality of the designed distributed logic controller. The theoretical approach is supplemented by the practical experiments. Furthermore, the proposed idea is illustrated by an example of a smart home system.

Application of hypergraphs in microcode length reduction of microprogrammed controllers

In the paper we propose a new method of the microinstruction length reduction in the designing process of microprogrammed controllers. The algorithm is based on the representation of the compatibility classes with hypergraphs. The whole process of the microinstruction length reduction is presented in details and illustrated by an example. Finally, proposed idea is compared with traditional solutions, based on the graph theory.

Dynamic Partial Reconfiguration of Concurrent Control Systems Implemented in FPGA Devices

A novel prototyping technique for concurrent control systems implemented in field programmable gate array (FPGA) devices is proposed in the paper. The method allows for dynamic modification of the implemented system. It means that the functionality of a part of the controller can be changed, while the rest of the system is still running. The approach applies to unified modeling language state machine diagrams as a specification of the system. Contrary to other methods, the presented concept requires neither major changes to the design, nor the application of external, specialized tools. The proposed idea has been experimentally verified with the use of Xilinx FPGAs.

Design of microprogrammed controllers with address converter implemented on programmable systems with embedded memories

In the paper the improvement of a traditional structure of a microprogrammed controller with sharing codes is discussed. The idea is based on the modification of internal modules and connections of the device. Such a solution permits to reduce the number of embedded memories needed for implementation of the microprogrammed controller on programmable structures, especially FPGAs.

Prototyping of Concurrent Control Systems With Application of Petri Nets and Comparability Graphs

This paper shows a novel prototyping technique for concurrent control systems described by interpreted Petri nets. The technique is based on the decomposition of an interpreted Petri net into concurrent sequential automata. In general, minimum decomposition requires runtime that is exponential in the number of Petri net places. We show that in many cases, including the real-life ones, the minimum decomposition problem can be solved in polynomial time. The proposed method allows implementing a concurrent control system using minimal number of sequential components, which requires polynomial time and can be applied to most of the considered cases. The presented concept is illustrated by a real-life industrial example of a beverage production and distribution machine implemented in a field programmable gate array.

Design of Multi-Context Reconfigurable Logic Controllers Implemented in FPGA Devices Oriented for Further Partial Reconfiguration

Reconfigurable systems have been recently used in many domains. Although the concept of multi-context logic controllers is relatively new, it may be noticed that the subject is receiving a lot of attention, especially in the industry. The work constitutes a stepping stone in design of reconfigurable logic controllers towards bridging the gap between Petri nets, their decomposition, formal verification and implementation with the use of FPGA structures with the possibility of further partial reconfiguration. The paper proposes a new design concept of reconfigurable logic controllers, implemented with the FPGA device. A logic controller is formally described by a Petri net and decomposed into separate sequential modules. Optional versions (contexts) of the selected module may be prepared additionally. Depending on the needs, a particular module can be replaced by either version (context) with the use of the partial reconfiguration technique. To avoid formal errors and mistakes, the proposed design path is s...

Dual synthesis of Petri net based dependable logic controllers for safety critical systems

In the paper, implementation of application specific logic controller for safety critical systems by means of Petri nets is described. The solution is based on duplicated main control unit and results comparison from both units. The design process of algorithm with use of Petri net is common for both unit. The hardware duplication is obtained during dual synthesis process. This process uses two different logic synthesis methods to obtain two different architectures for both control units. Such design flow simplify the process of realization of safety critical logic controllers.