Remigiusz Wiśniewski

Design of microprogrammed controllers to be implemented in FPGAs

Design of microprogrammed controllers to be implemented in FPGAs In the article we propose a new design method for microprogrammed controllers. The traditional structure is improved by modifying internal modules and connections. Such a solution allows reducing the total number of logic elements needed for implementation in programmable structures, especially Field Programmable Gate Arrays (FPGAs). Detailed results of experiments show that on the average the application of the proposed methods yields up to 30% savings as far as the destination device is considered.

Application of Hypergraphs to SMCs Selection

The paper deals with selection of State Machine Components (SMCs) based on Hypergraphs theory. The entire selection process use Petri nets as benchmarks. As it is known, Petri nets are used for modeling of concurrency processes. The SMCs selection problem is classified as NP-Hard which means there does not exist polynomial algorithm which provides an exact solution. In the article we show three SMCs selection methods, advantages and disadvantages of each, results of comparison between traditional methods (exponential backtracking, polynomial greedy) and an exact transversal method based on hypergraphs theory, their efficiency and propriety. An exact transversal method allows to obtain exact solution in polynomial time if selection hypergraph belongs to xt-hypergraph class.

Theoretical Aspects of Petri Nets Decomposition Based on Invariants and Hypergraphs

Two methods of Petri nets decomposition into State Machine Components (SMCs) are shown in the paper. The first one bases on the well-known algorithm of place invariants (p-invariants) calculation. The second method applies hypergraph theory and computation of exact transversals. The aim of the paper is theoretical analysis of the effectiveness of presented methods. We show, that despite the high popularity, the achieved results generated by p-invariants are not always correct and spurious components ought to be eliminated. Furthermore, the effectiveness of the application of hypergraphs into Petri net decomposition is analysed.

Partial reconfiguration of compositional microprogram control units implemented on FPGAS

Abstract The method of partial reconfiguration of Compositional Microprogram Control Units implemented on FPGAs is proposed. The method is based on the swapping of the content of Control Memory while the rest of the system is not modified. Such approach permits to decrease the size of a bit-stream that is sent to the device. Therefore time needed for device configuration is shorter. Proposed solution is much more safe due to less errors that can occur during reconfiguration of FPGAs. An example of proposed method application is discussed. The researches conducted by authors have shown that proposed method permits to decrease the size of a bit-stream that is sent to the device in comparison with traditional method even up to 95%.

Exact cover of states in the discrete state-space system

Given the discrete state-space system, the set cover problem is defined as selection of the minimal number of global states to cover all the local states. Commonly known methods base on the matrix reduction, boolean function transformation or heuristics ideas. Most of them are inefficient because of computational/memory complexity or non-optimal results. We propose an application of xt-hypergraphs to compute the solution in case where the discrete system can be represented by an xt-hypergraph. Recognition, as well as computation of exact cover in case of xt-hypergraphs is bounded by a polynomial in the number of local states. Therefore, the whole cover process problem turns out to be polynomial.

Effective Partial Reconfiguration of Logic Controllers Implemented in FPGA Devices

A method of partial reconfiguration of logic controllers implemented in FPGA is presented in the chapter. Only the control memory content is replaced while the rest of the system is not modified. The logic synthesis and implementation are performed only once. Therefore, such a realisation highly accelerates the whole prototyping process. The performed experiments showed that the original bit-stream that is sent to the FPGA can be reduced even over 500 times.

Partial reconfiguration of concurrent logic controllers implemented in FPGA devices

Reconfigurable systems are recently used in many domains. Although the concept of multi-context logic controllers is relatively new, it may be noticed that the subject is receiving a lot of attention, especially in the industry. The work constitutes a stepping stone in design of reconfigurable logic controllers implemented in an FPGA device. An approach of designing of logic controllers oriented for further partial reconfiguration is proposed. A case study of a milling machine is used for an illustration.

Design and verification of distributed logic controllers with application of Petri nets

The paper deals with the designing and verification of distributed logic controllers. The control system is initially modelled with Petri nets and formally verified against structural and behavioral properties with the application of the temporal logic and model checking technique. After that it is decomposed into separate sequential automata that are working concurrently. Each of them is re-verified and if the validation is successful, the system can be finally implemented.

Hardware realization of an SVM algorithm implemented in FPGAs

The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and “non-standard positions of control pulses” during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

IoT security with one-time pad secure algorithm based on the double memory technique

Secure encryption of data in Internet of Things is especially important as many information is exchanged every day and the number of attack vectors on IoT elements still increases. In the paper a novel symmetric encryption method is proposed. The idea bases on the one-time pad technique. The proposed solution applies double memory concept to secure transmitted data. The presented algorithm is considered as a part of communication protocol and it has been initially validated against known security issues.