Michel Pignol

An innovative open-loop CDR based on injection-locked oscillator for high-speed data link applications

A new fully integrated clock and data recovery (CDR) architecture based on an injection-locked oscillator is presented in this paper. Two circuits, implemented in CMOS VLSI technology and dedicated to 1 Gbps point-to-point networks, are detailed. This open-loop CDR topology is compared with classical ones (high-Q filter, phase-locking, ...) in term of power consumption, silicon area and complexity. Our circuits exhibit some major advantages versus traditional CDRs: no external component needed, low consumption and low locking time. It is a very simple way to achieve clock extraction and data regeneration for high-speed data link applications.

2-4 and 9-12 Gb/s CMOS fully integrated ILO-based CDR

A CDR dedicated to satellite data link is presented. The clock recovery function is made-up of an Injection Locked Oscillator combined with an analog phase alignment circuit. The circuit covers two bit-rate ranges: 2.2 to 4.3 Gb/s and 9.1 to 12.1 Gb/s. It was designed in 130 nm CMOS bulk process from STMicroelectronics. The overall power dissipation is 400 mW in the first bit-rate range and 480 mW in the second including 220 mW for I/O buffers. The eye opening at 10-9 of bit error rate is 940 mUI/440 mV at 3.1 Gb/s and 720 mUI/300 mV at 10.3 Gb/s.

SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link

Clock and data recovery (CDR) systems are the first logic blocks in serial data receivers and the latters performance depends on the CDR. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe is presented. The CDR uses an injection locked oscillator (ILO) which delivers the 100 GHz clock. The inherent phase shift between the recovered clock and the incoming data is compensated by a feedback loop which performs phase and frequency tracking. Furthermore, a windowed phase comparator has been used, first to lower the classical number of gates, in order to prevent any delay skews between the different phase detector blocks, then to decrease the phase comparator operating frequency, and furthermore to extend the ability to track zero bit patterns The measurements results demonstrate a 100 GHz clock signal extracted from 50 Gb/s input data, with a phase noise as low as 98 dBc/Hz at 100 kHz offset from the carrier frequency. The rms jitter of the 25 GHz recovered data is only 1.2 ps. The power consumption is 1.4 W under 2.3 V power supply.

A Heavy-Ion Tolerant Clock and Data Recovery Circuit for Satellite Embedded High-Speed Data Links

A clock and data recovery (CDR) circuit dedicated to satellite embedded high-speed data links is implemented in a 0.13 mum CMOS technology. Its radiation hardening is obtained thanks to an innovative architecture based on an injection-locked oscillator (ILO) associated with a phase-alignment circuit. Its low single-event transient (SET) sensitivity is shown thanks to heavy-ion and laser testing.

VHDL-AMS model of an injection locked VCO

A VHDL-AMS model of an injection locked voltage controlled oscillator is presented in this paper. The model is valid for any harmonic of the synchronization signal. Properties such as locking-range, bandwidth and settling time are taken into account. The model is used in mixed simulations to reduce the computation time. A comparison with a schematic LC oscillator shows very good correlation.

A 10-Gb/s CMOS fully integrated ILO-based CDR

A CDR circuit dedicated to satellite embedded data link is presented. This circuit combines an injection locked oscillator, with a phase alignment circuit, to achieve the clock recovery. The circuit was designed in a 130 nm CMOS process from STMicroelectronics. The working range is from 9.6 Gbit/s up to 10.2 Gbit/s, the power dissipation is 94 mW under 1.2 V power supply. The measured eye opening is 60 ps and 240 mV with a BER lower than 1012.

Windowed phase comparator for an 80Gbit/s CDR

High speed clock and data recovery (CDR) is a key component in future high speed communication link. In this paper an 80 Gbit/s CDR with a windowed phase comparator is presented. The CDR uses an Injection Locked Oscillator (ILO) and a PLL to lock the data frequency. The IC has been fabricated in a SiGe BiCMOS technology.