Michele G. Vieira

Using Bulk Built-in Current Sensors to Detect Soft Errors

Connecting a built-in current sensor in the design bulk of a digital system increases sensitivity for detecting transient upsets in combinational and sequential logic. SPICE simulations validate this approach and show only minor penalties in terms of area, performance, and power consumption

Modeling the sensitivity of CMOS circuits to radiation induced single event transients

An accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to radiation induced single event transients is presented. The key idea of the work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit to single event transients (SETs), without the need to run circuit level simulations. To accomplish this task, both single event transient generation and its propagation through circuit logic stages are characterized and modeled. The model predicts whether or not a particle hit generates a transient pulse which may propagate to the next logic gate or memory element. The electrical masking (attenuation) of the transient pulse as it propagates through each stage of logic until it reaches a memory element is also modeled. Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-Tools, intending to make automated evaluation of circuit sensitivity to SEU possible.

Single event transients in combinatorial circuits

The single event upset (SEU) mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time consuming and must be performed for each different circuit topology, incident particle and track. This work presents an accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to SEU. The key idea of this work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit, without the need to run circuit simulations. To accomplish the task, but single event transient generation and its propagation through circuit logic stages is characterized and modeled. The model predicts whether or not a particle hit generates a transient pulse (bit flip) which may propagate to the next logic gate or memory element. The propagation of the transient pulse through each stage of logic until it reaches a memory element is also modeled. Both duration and amplitude of the transient pulse are attenuated as it propagates through the logic gates. A simple, first order model for the degradation of a transient pulse as it is propagated through a chain of logic gates is also proposed. The model considers the electrical masking properties of the logic gates through which the pulse propagates. Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-tools, intending to make automated evaluation of MOS circuit sensitivity to SEU possible, as well as automated estimation of soft error rate

Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic

In this paper, we propose a new approach for using built-in current sensor (BICS) to detect not only transient upsets in sequential logic but also in combinational circuits. In this approach, the BICS is connected in the design bulk to increase its sensitivity to detect any current discrepancy that may occur during a charged particle strike. In addition, the proposed BICS can inform if the upset has occurred in the PMOS or NMOS transistors, which can generate a more precise evaluation of the corrupted region. The proposed approach was validated by Spice simulation. The BICS and the case-studied circuits were designed in the 100nm CMOS technology. The bulk BIC sensor detects various shapes of current pulses generated due to charged particle strike. Results show that the proposed bulk BICS presents minor penalties for the design in terms of area, performance and power consumption and it has high detection sensitivity

Generation and Propagation of Single Event Transients in CMOS Circuits

The generation and the propagation of radiation induced single event transients (SET) in CMOS circuits are evaluated. An accurate and computer efficient analytical model for SET generation and propagation is proposed. The model allows the rapid determination of the sensitivity of any MOS circuit node to SET, without the need to run circuit level simulations. The model predicts whether or not a particle hit generates a transient pulse which may propagate to the next logic gate or memory element. Electrical masking of the transient pulse as it propagates through each stage of logic until it reaches a memory element is also modeled. The proposed approach is suitable for integration into CAD-tools, intending to make automated evaluation of circuit sensitivity to SEU possible

Single event transients in dynamic logic

Radiation effects, like Single Event Transients (SET), are increasingly affecting integrated circuits as device dimensions are scaling down. With decreasing dimensions and supply voltages, the charge used to store information decreases, turning the circuits more sensitive to the transient currents generated by energetic particle hits. This is particularly important for dynamic logic, which relies on proper charge storage at circuit nodes.In this work the sensitivity of dynamic logic to Single Event Transients is studied and modeled. The single event upset (SEU) mechanism in both dynamic and static MOS circuits is studied starting from circuit simulation. From this study it is shown that standard dynamic logic circuits are much more sensitive to SET than static circuits. However, the implementation of a keeper technique may greatly reduce the sensitive of dynamic logic, increasing its robustness against SET.Furthermore, an accurate and computationally efficient analytical model for the evaluation of static and dynamic circuit sensitivity to SEU is presented. The model may be used in early design stages, helping to design circuits with increased tolerance to SET. The proposed model predicts whether or not a particle hit generates a SET which may be interpreted as a logical signal in the circuit. Good agreement between model and electrical simulation results is found.

Deterministic Methodology for Electrical Simulation of BTI Induced Pulse Broadening

This paper presents an analysis of the bias temperature instability (BTI) induced pulse broadening of single event transients (SETs) in inverter chains. A novel deterministic simulation methodology for BTI, using the trapping/de-trapping framework, is proposed and implemented in a commercial SPICE tool. The developed simulator properly predicts the possibility that an SET pulse may suffer propagation-induced pulse broadening (PIPB). The PIPB was analyzed in terms of supply voltage and input signal frequency. The simulations results are in agreement with experimental results from the literature.