Mihail Jefremow

Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS

Spin-torque-transfer (STT) MRAM is a promising candidate for embedded non-volatile memory in next generation microcontrollers, because of superior endurance, low process costs and logic supply voltage operation. Two major drawbacks of STT-MRAM technology are the small read window because of the low tunnel magnetic resistance (TMR) ratio, and the low read current due to read disturb, which is proportional to the bitline (BL) voltage [1].

Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive

This paper presents a BL-capacitance-cancelation sensing scheme implemented in a 65nm embedded FLASH technology to overcome the speed limitations of conventional voltage sensing. It is combined with a continuous precharge scheme as described in to increase the robustness of the system supporting the low-swing-sensing phase.

Slope only sense amplifier with 4.5ns sense delay for 8Mbit memory sector, employing in situ current monitoring with 66% write speed improvement in 40nm embedded flash for automotive

This paper proposes two new design techniques, the slope sense amplifier (S-SA) circuit combined with in situ current monitoring (ISCM) implemented in a 40nm embedded FLASH technology. S-SA reduces the sense delay time below 4.5ns thereby enabling a sub 10ns read access time operation for an 8Mbit memory sector. It also provides a power reduction of more than 40% and reduces the occupied area of the sensing circuits by 50%. The S-SA enables a reduced signal development time on the BL increases the read window by 50%. In addition the ISCM improves the write performance by a factor of at least 1.6.