Ullrich Menczigar

Circuit configuration for enabling a clock signal in a manner dependent on an enable signal

Semiconductor memory with a clock synchronization device having a temperature controlled delay circuit

SELF TIMED CURRENT INTEGRATING SCHEME EMPLOYING LEVEL AND SLOPE DETECTION

Circuit configuration for setting the input resistance and the input capacitance of an integrated semiconductor circuit chip

Digital memory circuit having a plurality of memory banks

Eigengetaktetes, Pegel- und Steilheitserkennung einsetzendes Stromintegrationsschema

Self-timed, level and slope detection onset of current integration scheme

Sense amplifier circuit and method for reading a memory cell

Elektronische Schaltungsanordnung mit aktiver Regelung bei einem Empfang eines elektrischen Empfangssignals

Receiver circuit, for relaying data signals e.g. for computer and software applications, uses two inputs for coupling external digital data signal into receiver circuit