Stephen F. Geissler

A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects

A 32 b 480 MHz PowerPC reduced-instruction-set-computer (RISC) microprocessor is migrated into an advanced 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors. These technology features have helped to increase the microprocessor internal clock frequency to 480 MHz at 2.0 V and 85/spl deg/C, and at the fast end of the process distribution. When operating at room temperature, the clock frequency increases to over 500 MHz. The microprocessor architecture includes two 32 KB L1 caches, one for data and one for instructions, integrated L2 cache controller working with L2 caches of 256 KB, 512 KB, or 1MB, and I/Os interfacing with the external bus using industry-standard 3.3 V. The microprocessor is implemented in 2.5 V CMOS technology and has migrated to 1.8 V CMOS technology.

Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks

The impact of MOSFET source/drain junction scaling on the ESD robustness of shallow trench isolation (STI)-defined diode structures is shown for the first time. ESD robustness improvements to STI-bound p/sup +/ diodes using germanium preamorphization and deep B11 implants, and polysilicon-bordered ESD networks are also discussed.

A 580 MHz RISC microprocessor in SOI

A RISC microprocessor remapped in SOI technology exploits the advantages of SOI to boost processor frequency by 20% to 580MHz at 2.0V and 85/spl deg/C and fast process. The separation by implanted oxygen (SIMOX) SOI process produces partially-depleted devices. Source and drain capacitances are reduced by an order of magnitude, improving gate delay by 12%. Reduction in body-bias effects on device stacks and passgate topologies results in an additional 15%-25% improvement. Speed gains of up to 35% are achieved in some designs. The frequency-limiting paths in this processor are dominated by SRAM access and self-timed dynamic circuits whose timing had to be relaxed to guarantee functionality.

A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric

Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.

A new three-dimensional MOSFET gate-induced drain leakage effect in narrow deep submicron devices

A new MOSFET gate-induced drain leakage (GIDL) mechanism is observed in narrow-width trench-isolated MOSFET devices. Electrical measurements and device simulation show that this mechanism occurs due to electric-field enhancement at the three-dimensional intersection of the gate-to-drain overlap region and the trench corner. The enhanced electric field increases the GIDL current at the 3-D intersection region. This imposes another fundamental limit on MOSFET dielectric scaling in deep submicron narrow-width devices. Since the 3-D GIDL mechanism is caused by a high electric field, trench corner rounding and lightly doped drain junctions provide effective solutions.<<ETX>>

A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features

The first two members in a family of 64-bit superscalar microprocessors are presented. The 130-nm processor, which was introduced first, offers 5-way instruction dispatch, support for 4-way integer and floating-point single-instruction multiple-data (SIMD) operations, a 512-kB second level (L2) cache, and a high-speed external bus. The 90-nm processor is a technology remap of the 130-nm design. It retains the features of the 130-nm processor and adds others, including a new power management facility. The architecture, device characteristics, power management, and thermal details of these two processors are described. In addition, the dataflow layout, aspects of the circuit design, clocking, and timing are discussed.

A 64B CPU Pair: Dual- and Single-Processor Chips

Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The single-processor chip shares the duals basic core and cache design

A thermally activated gate current in off-state PMOSFETs

Using buried-channel PFET devices with lightly doped drains (LDDs), the authors study the gate current and the threshold-voltage instability at intermediate electric fields and as a function of temperature. Although the same effects occur on surface-channel devices, larger potential differences were required because the built-in potential difference between N+ and P+ diffusions increases gate-induced diffusion leakage (GIDL) in buried-channel devices. Gate current was measured over a wide range of voltage and temperature on large gate perimeter PMOSFET devices. The measurements revealed a gate current with a voltage and temperature dependence proportional to the GIDL current. Hot electron stressing suggests the trapped charge is located near the gate-drain overlap region for short channel devices and near the intersection of the gate-drain overlap and the trench convex corner for narrow trench isolated devices.<<ETX>>

Timing driven wiring on an advanced microprocessor

The effect of wire delay within critical timing paths is becoming an increasing problem. By comparing the large improvement of transistor performance, due to shrinking L/sub eff/ or new technology such as silicon on insulator, versus the smaller improvements of wire delay, such as copper wires and better dielectrics, it can be seen that the wiring within an advanced microprocessor will become a more dominant portion of the critical paths. In deep sub-micron designs it is crucial to analyze and improve any wire dominated paths while assuming that the transistor delay continues to improve. This paper describes wire related improvements, such as an algorithmic wiring approach, wire bending and clock skew reduction that is used in the timing convergence of an advanced PowerPC microprocessor. The impact of wiring improvements is evaluated on the timing, clocking and wireability of the microprocessor.