Milos Stanisavljevic

Optimization of nanoelectronic systems' reliability under massive defect density using cascaded R-fold modular redundancy

The theoretical analysis of R-fold modular redundancy, cascaded R-fold modular redundancy and NAND multiplexing is presented and these fault-tolerant techniques are compared in terms of resistance to massive levels of defect density. Optimal cluster size analysis and redundancy optimization of the cascaded R-fold modular redundancy technique has been performed for the first time in the context of a large-scale system. The optimal window of application of each fault-tolerant technique with respect to defect density is presented as a way to find the optimum design trade-off between the reliability and power/area. Building viable systems consisting of components with high defect densities in future nanoscale technologies will have a high cost in power/area, regardless of the fault-tolerant techniques used.

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

This paper presents a method enabling the evaluation of the averaging fault-tolerant technique, using the output probability density functions of unreliable units that are acquired from Monte Carlo simulations. The method has been verified by comparing numerical simulations and analytical developments. A fault-tolerant four-layer architecture using averaging and with both fixed and adaptable threshold is compared with triple and R-fold modular redundancy (RMR) techniques, at gate level and using fault-free decision gates, showing that the redundancy factor can be reduced by a factor of two to three using the proposed four-layer architecture, in replacement of RMR, thus enabling significant savings in the area, and power dissipation. The analysis of the reliability of averaging techniques together with the redundancy optimization has been performed for the first time in the context of a large-scale system, showing that a target reliability can be achieved with low redundancy factors (R < 8) for moderate defect densities (device failure rate up to 10-5). The performed analysis of the optimal size of the reliable islands (clusters) supports the assumption that clustering needs to be applied at the lower levels of design abstraction hierarchy, especially for fabrication technologies with increased defect density.

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

An assessment of the fault-tolerance properties of single-ended and differential signaling is shown in the context of a high defect density environment, using a robust error-absorbing circuit architecture. A software tool based on Monte-Carlo simulations is used for the reliability analysis of the examined logic families. A benefit of the differential circuit over standard single-ended is shown in case of complex systems. Moreover, analysis of reliability of different circuits and discussion on the optimal granularity of redundant blocks was made.

Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)

The theoretical analysis of R-fold modular redundancy with distributed voters -- distributed R-fold modular redundancy, in terms of reliability is presented for the first time to the best of authors knowledge. This technique is compared in terms of resistance to massive levels of defect density expected in future nano-devices to R-fold modular redundancy with a single voter, cascaded R-fold modular redundancy and NAND multiplexing. Optimal partition size analysis and redundancy optimization of distributed R-fold modular redundancy technique has been performed for the first time in the context of a large-scale system. The optimal window of application of different fault-tolerant techniques with respect to defect density is presented as a way to find the optimum design trade-off between the reliability and power/area.

A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on A-Priori Functional Fault-Tolerance Analysis

This paper presents a new approach for monitoring and estimating device reliability of nanometer-scale devices prior to fabrication. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. A complete tool for a-priori functional fault tolerance analysis was developed. It is a statistical Monte Carlo based tool that induces different failure models, and does subsequent evaluation of system reliability under realistic constraints. A structured fault modeling architecture is also proposed, which is together with the tool a part of the new design method where reliability is considered as a central focus from an early development stage.

Selective redundancy-based design techniques for the minimization of local delay variations

In this paper a novel approach to optimize digital integrated circuits yield with regards to speed and area/power for aggressive scaling technologies is presented. The technique is intended to reduce the effects of intra-die variations using redundancy applied only on critical parts of the circuit. The inherent property of the technique is that the improvement in the maximum frequency the circuit can run is higher for the larger variations. The work shows that the technique can be already applied for 65nm CMOS technology process where a beneficial delay vs. area/power tradeoff can be made. However, a significant benefit is expected for future nanoscale CMOS technologies such as 45nm and 32nm nodes and in low-voltage applications.

Analysis of reliability in nanoscale circuits and systems based on a-priori statistical fault-modeling methodology

This paper presents a new approach for monitoring and estimating device reliability of nanometer-scale devices prior to fabrication. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. A complete Monte Carlo based tool for a-priori functional fault tolerance analysis was developed, that induces different failure models, and does subsequent evaluation of system reliability under realistic constraints. A structured fault modeling architecture is also proposed, which is together with the tool a part of the new reliability design method representing a compatible improvement of existing IC design methodologies

Reliability, Faults, and Fault Tolerance

A clear understanding of several concepts and terminology related to reliability is needed to proceed with the understanding of the methodologies which are applied to guarantee optimal operability of VLSI systems, fault tolerance, and circuit architectures implementing them. Basic terms such as reliability, fault tolerance, faults, and fault modeling are introduced and explained in detail.

Nanotechnology and Nanodevices

The end of the ITRS roadmap for classical CMOS devices and circuits envisions the emergence of future nanotechnologies and nanodevices and also evidences many new related challenges. This chapter covers some of these issues using a tutorial presentation style.

Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS

As already explained in the introduction to Chap. , the development of economically feasible nanoelectronic systems requires a tight interplay between materials and fabrication technologies on the one hand and design technologies on the other. In particular, it is quite essential to explore circuit-level measures to mitigate the limitations of process variations (PVs), leakage, and reduced device reliability and, finally, to explore system-level design approaches that are better adapted to the constraints imposed by the materials, technology, and device physics. This chapter largely deals with some of these key questions that relate to design technologies for nanoelectronic systems.