Ming-Che Hsieh

Thermo-mechanical simulative study for 3D vertical stacked IC packages with spacer structures

As the market demands for high performance, miniaturized, better reliability and lower-priced portable electronic products, the integration of a system into three-dimensional (3D) chip stacking packages are presently used to achieve these targets. Even though the miniaturization of system scaling, low power consumption and better electrical performance can be performed by 3DIC packaging technologies, thermo-mechanical problems occur due to the 3D stacking feature. Because dice are vertically stacked in 3DIC packages, higher junction temperature as well as temperature concentration phenomenon inside the stacking dice are resulted in and cause larger corresponding thermal induced stresses. Hence, the problems of heat dissipation and thermal induced stresses always cause failures or fatigues in 3D stacked IC packages and become critical reliability issues. In order to realize thermo-mechanical coupling effects in 3D vertical stacked IC packages with spacer structures, four layer vertical stacked dice (bare die to bare die) with TSV (through-silicon-via), metal bumps, and spacer structures are constructed as the test vehicle. In the thermo-mechanical coupling simulative study, the accurate convection heat transfer coefficients that obtained from computational fluid dynamics technique are used as the applied boundary conditions in finite element analysis (FEA) modeling to obtain precisely thermal stress distributions. Therefore, not only the temperature distributions and thermal characteristics (thermal resistance and junction temperature) can be resolved but also the corresponding precisely thermal stress distributions can be illustrated by using FEA. These results can be most effectively used as design guidelines to engineers if thermo-mechanical coupling solutions for 3D vertical stacked IC package with the conditions of dice powered on are required.

Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO2, the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

Thermo-mechanical analysis of thermoelectric modules

The present paper studies the thermo-mechanical performance of thermoelectric modules by utilizing the Finite Element Analysis FEA simulation software ANSYS. A typical type TEG device with 32 pairs of legs was constructed. Three different thickness for the pads with 100um, 500um, and 1000um were given for investigating the geometry effect. The thermo-electric results got well confirmed compared with analytical solution. The maximum Von Mises stress occurs on the contact surface between top pad and top substrate due to the large CTE mismatch between the copper pad and the A1N substrate, especially in the higher temperature case. This stress might lead to module failure and reduce the reliability.

Nonlinear thermal stress analyses and design guidelines for through silicon vias (TSVs) in 3D IC integration

In this investigation, a set of empirical equations which predicts the maximum thermal stresses at the vicinity of a copper filled TSV for 3D IC integration has been proposed. The finite element model of a symmetrical single in-line TSV with redistribution layer has been created at first and the parametric study includes the TSV diameter, pitch, and thickness, and the thickness of SiO2 passivation and Cu seed layer. The methodology of design of experiments (DOE) has been adopted to deliver a set of empirical equations which captures the most important mechanical parameters of TSVs to comprehend the corresponding thermal stress and strain responses. Through this set of empirical equations, the estimated maximum thermal stresses and strains for different TSV diameter (from 10μm to 50μm) can be explained and the significant geometrical parameters can be easily observed. In addition, based on the present parametric study and results, a set of design guidelines for optimizing the mechanical performance of copper filled TSV in 3D IC integration has been proposed. These results are helpful to engineers if thermal stress solutions for TSVs in 3D IC integration are required.

Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration

The technology of 3-D IC integration is expected to satisfy the demand for high-performance, better reliability, miniaturization, and lower priced portable electronic products. Since through silicon via (TSV) is at the heart of 3-D IC integration architectures, the reliability issues with TSV interconnects are an area of extreme concern. Due to the large thermal expansion mismatch among the copper (Cu), silicon die, and silicon dioxide (SiO2) dielectric layer, the induced thermal stresses and strains can occur and become the driving forces that cause failures in TSV interconnects. Hence, thermomechanical stress analyses and failure mode investigations for TSVs are in urgent need. Among the typical failures, delamination is the mostly common failure type, which is caused when lower energy release rate (ERR) or higher critical stresses at interfaces are present. In this paper, the finite element analysis (FEA) for a symmetrical single inline Cu-filled TSV with redistribution layer is illustrated and has been used to realize the thermomechanical stress distribution for TSVs in 3-D IC integration. Moreover, four kinds of interfacial cracks that were embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad and TSV wall delamination cases) and the critical stress areas observed from FEA are introduced to estimate the interfacial ERR using modified virtual crack closure technique. The parametric study has also been adopted to capture the most important mechanical factors of the TSVs to comprehend the corresponding ERR. The significance of discussed parameters such as crack length, TSV diameter, TSV pitch, TSV depth, SiO2 thickness, and Cu seed layer thickness are also examined. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3-D IC integration.

Thermal Stress Analysis of Cu/Low-k Interconnects in 3D-IC Structures

The topics of 3D-IC packages are now widely studied around the world in recent years, not only in electronic packaging areas, but also in bioengineering areas and so on. With the developments of 3D-ICs technologies, packaging effects on 3D-ICs of Cu/low-k interconnects have become a critical reliability issue, especially in the assembly processes and reliability test procedures. In 3D-IC packages, low-k dielectrics are now popularly used to retard the RC delayed effects, increase the bandwidth, reduce the inductance and decrease the power consumption. By using the weaker low-k dielectrics instead of traditional TEOS interlevel dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed that raising serious reliability concerns for Cu/low-k chips. In this paper, the thermal induced stresses of Cu/low-k interconnect in 3D-IC structures during reliability test process are obtained by three-dimensional finite element analysis. The packaging induced crack in Cu/low-k structures is also studied. The results show that the interfacial cracks in 3D-ICs significantly impact the distribution of thermal induced stresses in Cu/low-k structures and could have prominent influence on their reliability